1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 20 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Orig
2、inal date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CMOS, 1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09619 YY-MM-DD 09-04-06 REV PAGE 1 OF 20 AMSC N/A 5962-V032-09 Provided by IH
3、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 1:3 LVPECL clock buffe
4、r with programmable divider microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on
5、 the engineering documentation: V62/09619 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 CDCP1803-EP 1:3 LVPECL clock buffer with programmable divider 1.2.2 Case outline(s). The case outli
6、ne(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 24 JEDEC MO-220 Plastic quad flatpack, no-leads 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot sold
7、er dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 3 1.3 Absolute maxim
8、um ratings. 1/ Supply voltage range (VDD) . -0.3 V to 3.8 V Input voltage range (VI). -0.2 V to VDD+0.2 V Output voltage range (VO) . -0.2 V to VDD+0.2 V Differential short-circuit current, Yn, Yn (IOSD) . Continuous Electrostatic discharge (ESD) rating: Human body model (HBM) (1.5 k, 100pF) 2000 V
9、Maximum junction temperature (TJ) 150C 2/ Storage temperature range (TSTG). -65C to +150C 1.4 Recommended operating conditions. Supply voltage range (VDD) . 3 V to 3.6 V Operating free-air temperature range (TA). -55C to +125C Operating Life Derating Chart _ 1/ Stresses beyond those listed under “ab
10、solute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for e
11、xtended periods may affect device reliability. 2/ Silicon operating life design goal is 10 years at 105C junction temperature ( does not include package interconnect life). See Operating Life Derating Chart for information. Provided by IHSNot for ResaleNo reproduction or networking permitted without
12、 license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices JESD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surfac
13、e Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as show
14、n in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The
15、maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The
16、 case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure
17、4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 5a -5d. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 5 TABLE I. Elec
18、trical performance characteristics. 1/ Limits Test Symbol Conditions VDDTemperature, TADevice type Min Max Unit LVPECL input IN, IN Input frequency fclk0 800 MHz High level input common mode voltage VCM1 VDD 0.3 V 2/ 500 1300 Input voltage swing between IN and IN VIN3/ 125 mV Input current IINVIN= V
19、DDor 0 V 10 A Input impedance RIN300 k Input capacitance at IN, IN CI3 V to 3.6 V 25C, -55C to 125C All 1 TYP pF LVPECL output driver Y2:0, Y2:0 Output frequency fclkSee figure 5a. 0 800 MHz High level output voltage VOHTermination with 50 to VDD 2 V VDD 1.18 VDD 0.81 V Low level output voltage VOLT
20、ermination with 50 to VDD 2 V VDD 1.98 VDD 1.55 V Output voltage swing between Y and Y VOSee figure 5a. Termination with 50 to VDD 2 V 3 V to 3.6 V 500 mV IOZLVO= 0 V 5 Output 3-state current IOZHVO= VDD 0.8 V 3.6 V 10 A Rise and fall times tr/ tfSee figure 5b. 20% to 80% of VOUTPP170 400 ps Output
21、skew between any LVPECL output Y2:0 and Y2:0 tskpecl(o)4/ 70 Output duty cycle distortion tDUTY5/ Crossing point-to-crossing point distortion -50 50 ps Part-to-part skew tsk(pp)Any Y. 6/ 50 TYP ps Output capacitance COVO= VDDor GND 1 TYP pF Expected output load LOAD 3 V to 3.6 V 25C, -55C to 125C Al
22、l 50 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 6 TABLE I. Electrical performance characteristics - Continue
23、d. 1/ Limits Test Symbol Conditions VDDTemperature, TADevice type Min Max Unit LVPECL input-to-LVPECL output parameters Propagation delay, rising edge tpd(lh)See figure 5c. VOX to VOX 320 600 ps Propagation delay, falling edge tpd(hl)See figure 5c. VOX to VOX 320 600 ps LVPECL pulse skew tsk(p)See f
24、igure 5c. VOX to VOX 7/ 3 V to 3.6 V 25C, -55C to 125C All 100 ps Jitter characteristics See figure 5d. 12 kHz to 20 MHz, fout= 250 MHz to 800 MHz, divide-by-1 mode 0.15 TYP Additive phase jitter from input to LVPECL output Y2:0 tjitterLVPECLSee figure 5d. 50 kHz to 40 MHz, fout= 250 MHz to 800 MHz,
25、 divide-by-1 mode 3 V to 3.6 V 25C, -55C to 125C All 0.25 TYP ps rmsSupply current electrical characteristics Full load. f = 800 MHz for LVPECL outputs, All outputs enabled and terminated with 50 to VDD 2 V on LVPECL outputs. 3.3 V 140 TYP Supply current No load. f = 800 MHz for LVPECL outputs, Outp
26、uts enabled, no output load. 3.6 V 90 Supply current saving per LVPECL output stage disabled, no load IDDf = 800 MHz for LVPECL output 3.3 V 10 TYP mA Supply current, 3-state IDDZf = 0 Hz, All outputs in high-impedance state by control logic. 3.6 V 25C, -55C to 125C All 0.5 mA See footnotes at end o
27、f table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Condit
28、ions VDDTemperature, TADevice type Min Max Unit Package thermal resistance Package thermal resistance 8/ RJA-14-layer JEDEC test board (JESD51-7), airflow = 0 ft/min 106.6 TYP C/W Package thermal resistance with thermal vias in printed circuit board 8/ RJA-24-layer JEDEC test board (JESD51-7) with f
29、our thermal vias of 22-mil diameter each, airflow = 0 ft/min All 55.4 TYP C/W Control input characteristics Setup time, S0, S1, S2, and EN terminals before clock IN tsu25 ns Hold time, S0, S1, S2, and EN terminals after clock IN th0 ns Time between latching the EN low transition and when all outputs
30、 are disabled (how much time is required until the outputs turn off) t(disable)10 TYP ns Time between latching the EN low-to-high transition and when outputs are enabled based on control settings (how much time passes before the outputs carry valid signals) t(enable)1 TYP s Internal pullup resistor
31、on S2:0 and EN input Rpullup 60 TYP k Three-level input high, S0, S1, S2, and EN terminals 9/ VIH(H)0.9VDDV Three-level input low, S0, S1, S2, and EN terminals VIL(L)0.1VDDV Input current high, S0, S1, S2, and EN terminals IIHVI= VDD-5 A Input current low, S0, S1, S2, and EN terminals IILVI= GND 3 V
32、 to 3.6 V 25C, -55C to 125C All 38 85 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 8 TABLE I. Electrical perform
33、ance characteristics - Continued. 1/ Limits Test Symbol Conditions VDDTemperature, TADevice type Min Max Unit Bias voltage VBB Output reference voltage VBB IBB= -0.2 mA 3 V to 3.6 V 25C, -55C to 125C All VDD 1.4 VDD 1.1 V 1/ Testing and other quality control techniques are used to the extent deemed
34、necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization an
35、d/or design. 2/ Is required to maintain ac specifications. 3/ Is required to maintain device functionality. 4/ Output skew, tsk(o), is calculated as the greater of: - The difference between the fastest and the slowest tpd(LH)n(n = 0. . . 2). - The difference between the fastest and the slowest tpd(H
36、L)n(n = 0. . . 2). 5/ For an 800 MHz signal, the 50 ps error would result in a duty cycle distortion of 4% when driven by an ideal clock input signal. 6/ Part-to-part skew, tsk(pp), is calculated as the greater of: - The difference between the fastest and the slowest tpd(LH)n(n = 0. . . 2 for LVPECL
37、, n = 3 for LVCMOS) across multiple devices. - The difference between the fastest and the slowest tpd(HL)n(n = 0. . . 2 for LVPECL, n = 3 for LVCMOS) across multiple devices. 7/ Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and th
38、e low-to-high (tpd(LH) propagation delays when a single switching input causes one or more outputs to switch, tsk(p)= | tpd(HL) tpd(LH)|. Pulse skew is sometimes referred to as pulse width distortion or duty cycle skew. 8/ It is recommended to provide four thermal vias to connect the thermal pad to
39、the package effectively with the printed circuit board (PCB) and ensure a good heat sink. 9/ Leaving this terminal floating automatically pulls the logic level high to VDDthrough an internal pullup resistor of 60 k. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
40、 from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 9 Case X NOTES: 1. This drawing is subject to change without notice. 2. Falls within JEDEC MO-220. 3. All linear dimensions are shown in millimeters. 4. Quad flatpack, no-leads (QFN) p
41、ackage configuration. 5. The package thermal pads must be soldered to the board for thermal and mechanical performance. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE
42、 IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 10 Case X Dimensions Millimeters Symbol Min Max A 1.00 1.80 A1 0.00 0.05 A2 0.20 REF b 0.18 0.30 D/E 3.85 4.15 D1/E1 2.00 2.20 e 0.50 TYP e1 2.50 TYP S 0.30 0.50 FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking
43、 permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09619 REV PAGE 11 Terminal Functions Terminal Name No. I/O Description EN 1 I (with 60 k pullup) ENABLE: Enables or disables all outputs simultaneously. En = 1: Outputs on a
44、ccording to S2:0 settings. EN = 0: Outputs Y2:0 off (high impedance) See Selection Mode Table for details. IN, IN 3, 4 I (differential) Differential input clock. Input stage is sensitive and has a wide common-mode range. Therefore, almost any type of differential signal can drive this input (LVPECL,
45、 LVDS, CML, HSTL). Because the input is high-impedance, it is recommended to terminate the PCB transmission line before the input (e.g., with 100 across the input). Input can also be driven by a single-ended signal if the complimentary input is tied to VBB. The inputs employ an ESD structure protect
46、ing the inputs in case of an input voltage exceeding the rails by more than 0.7 V. Reverse biasing of the device through these inputs is possible and must be prevented by limiting the input voltage VDD. NC 12 No connection. Leave this terminal open or tie to ground. S2:0 18, 19, 24 I (with 60 k pull
47、up) Select mode of operation. Defines the output configuration of Y2:0, see Selection Mode Table for configuration. VBB 6 O Bias voltage output can be used to bias unused complementary input IN for single-ended input signals. The output voltage of VBB is VDD 1.3 V. When driving a load, the output cu
48、rrent drive is limited to about 1.5 mA. VDDPECL 2, 5 Supply Supply voltage PECL input + internal logic. VDD2:0 8, 11, 14, 17, 20, 23 Supply PECL output supply voltage for output Y2:0. Each output can be disabled by pulling the corresponding VDDx to GND. CAUTION: In this mode, no voltage from outside
