1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE 40 41 42 43 44 45 46 47 REV PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY
2、 Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICROCONTROLLER, MONOLITHIC SILICON 09-07-21 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09620 REV PAG
3、E 1 OF 47 AMSC N/A 5962-V033-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirement
4、s of a high performance mixed signal microcontroller microcircuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number fo
5、r identifying the item on the engineering documentation: V62/09620 - 01 X A Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 MSP430F2618-EP Mixed signal microcontroller 1.2.2 Case outline(s). The cas
6、e outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 113 JEDEC MO-225 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder
7、 dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other 1.3 Absolute maximum ratings. 1/ Voltage applied at VCCto VSS. -0.3 V to 4.1 V Voltage applied to any pin -0.3 V to VCC+ 0.3 V 2/ Diode current at any device terminal 2 mA Storage temperature range, TSTG(Unprogrammed devic
8、e) -55C to 150C 3/ Storage temperature range, TSTG(Programmed device) -40C to 105C 3/ _ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions be
9、yond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltages referenced to VSS. The JTAG fuse blow voltage, VFB, is allowed to exceed the absolute maximum rating. The vo
10、ltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. 3/ Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Pro
11、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 3 1.4 Recommended operating conditions. Supply voltage during program execution (VCC) . 1.8 V to 3.6 V
12、4/ Supply voltage during flash memory programming (VCC) . 2.2 V to 3.6 V 4/ Supply voltage (VSS) . 0.0 V 5/ Processor frequency fSYSTEMrange (Maximum MCLK frequency): 6/ 7/ See figure 4. VCC= 1.8 V, Duty Cycle 50% 10% dc to 4.15 MHz VCC= 2.7 V, Duty Cycle 50% 10% dc to 12 MHz VCC 3.3 V, Duty Cycle 5
13、0% 10% dc to 16 MHz Operating free air temperature range, TA. -40C to 105C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC J-STD-020 Joint IPC/JEDEC standard for moisture/reflow sensitivity classification for nonhermetic solid state surface mount
14、 devices. (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.
15、3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum
16、 and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. _ 4/ AVCC= DVCC= VCC. It is recommended to p
17、ower AVCCand DVCCfrom the same source. A maximum difference of 0.3 V between AVCCand DVCCcan be tolerated during power-up. 5/ AVSS= DVSS= VSS. 6/ The CPU is clocked directly with MCLK. 7/ Modules might have a different maximum input clock specification. Refer to the data sheet from the manufacturer.
18、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 4 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2
19、 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Operating area. The operating area shall be as shown in figure 4. 3.5.5 Active mode supply current. The active mode supply
20、current shall be as shown in figure 5. 3.5.6 POR/Brownout reset. The POR/Brownout reset shall be as shown in figures 6 -8. 3.5.7 Test circuits and timing waveforms. The test circuits and timing waveforms shall be as shown in figures 9-24. Provided by IHSNot for ResaleNo reproduction or networking pe
21、rmitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max Active mode supply current in
22、to VCCexcluding external current 3/ 4/ See figure 5. Active mode (AM) current (1 MHz) IAM, 1 MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32,768 Hz, Program executes from flash, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40C to 85C 2.2 V 395 A 105C 420 -40C to 8
23、5C 3 V 560 105C 595 Active mode (AM) current (1 MHz) IAM, 1 MHzfDCO= fMCLK= fSMCLK= 1 MHz, fACLK= 32,768 Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40C to 85C 2.2 V 370 A 105C 390 -40C to 85C 3 V 495 105C 520 Active mode (AM)
24、current (4 kHz) IAM, 4 kHzfMCLK= fSMCLK= fACLK= 32,768 Hz/8 = 4096 Hz, fDCO= 0 Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCGO = 0, SCG1 = 0, OSCOFF = 0 -40C to 85C 2.2 V 9 A 105C 31 -40C to 85C 3 V 11 105C 32 Active mode (AM) current (100 kHz) IAM,
25、100 kHzfMCLK= fSMCLK= fDCO(0,0) 100 kHz, fACLK= 0 Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCGO = 0, SCG1 = 0, OSCOFF = 1 -40C to 85C 2.2 V 86 A 105C 99 -40C to 85C 3 V 107 105C 128 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permi
26、tted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max Low-power mode supply
27、current into VCCexcluding external current 3/ 4/ Low power mode 0, (LPM0) current 5/ ILPM0, 1 MHzfMCLK= 0 MHz, fSMCLK= fDCO= 1 MHz, fACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 -40C to 85C 2.2 V 83 A 105C 98 -40C to 85C 3 V 105 105C 125 Lo
28、w power mode 0, (LPM0) current 5/ ILPM0, 100 kHzfMCLK= 0 MHz, fSMCLK= fDCO(0,0) 100 kHz, fACLK= 0 Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCGO = 0, SCG1 = 0, OSCOFF = 1 -40C to 85C 2.2 V 49 A 105C 62 -40C to 85C 3 V 55 105C 73 Low power mode 2 (LPM2) current 6/ ILPM2fMCLK= fSMCLK= 0 MHz, fDCO= 1 MHz, f
29、ACLK= 32,768 Hz, BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 -40C to 85C 2.2 V 33 A 105C 46 -40C to 85C 3 V 36 105C 55 Low power mode 3 (LPM3) current 6/ ILPM3, LFXT1fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 32,768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 -
30、40C 2.2 V 1.2 A 25C 1.3 85C 7 105C 24 -40C 3 V 1.3 25C 1.5 85C 8 105C 30 Low power mode 3 current (LPM3) 6/ ILPM3, VLOfDCO= fMCLK= fSMCLK= 0 MHz, fACLKfrom internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 -40C 2.2 V 1.0 A 25C 1.0 85C 6.5 105C 24 -40C 3 V 1.2 25C 1.2 85C 7.5 1
31、05C 29.5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 7 TABLE I. Electrical performance characteristics Continued.
32、 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max Low-power mode supply current into VCCexcluding external current - Continued. 3/ 4/ Low power mode 4 current (LPM4) 7/ ILPM4fDCO= fMCLK= fSMCLK= 0 MHz, fACLK= 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 -40C 2.2 V
33、 0.5 A 25C 0.5 85C 6 105C 23 -40C 3 V 0.5 25C 0.5 85C 7 105C 24 Schmitt-trigger inputs - ports P1 through P8, RST/ NMI, JTAG, XIN, and XT2IN 8/ Positive-going input threshold voltage VIT+-40C to 105C 0.45 x VCC0.75 x VCCV 2.2 V 1.0 1.65 3 V 1.35 2.25 Negative-going input threshold voltage VIT-40C to
34、 105C 0.25 x VCC0.55 x VCCV 2.2 V 0.55 1.2 3 V 0.75 1.65 Input voltage hysteresis (VIT+ - VIT-) Vhys -40C to 105C 2.2 V 0.2 1.0 V 3 V 0.3 1.0 Pullup/Pulldown resistor RPullPullup: VIN= VSS, Pulldown: VIN= VCC-40C to 105C 20 50 k Input capacitance CIVIN= VSSor VCC-40C to 105C 5 TYP pF Input - ports P
35、1 and P2 External interrupt timing t(int)Port P1, P2: P1.x to P2.x, external trigger pulse width to set interrupt flag. 9/ -40C to 105C 2.2 V/ 3 V 20 ns Leakage current - ports P1 through P8 High-impedance leakage current Ilkg(Px.x)10/ 11/ -40C to 105C 2.2 V/ 3 V 50 nA Standard inputs RST /NMI Low-l
36、evel input voltage VIL-40C to 105C 2.2 V/ 3 V VSSVSS+ 0.6 V High-level input voltage VIH-40C to 105C 2.2 V/ 3 V 0.8 x VCCVCCV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHI
37、O SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max Outputs - ports P1 through P8 High-level output voltage VOHIOH(max) = -1.5 mA 12/ -40C to 105C 2.2 V
38、VCC 0.25 VCCV IOH(max) = -6 mA 13/ VCC 0.6 VCCIOH(max) = -1.5 mA 12/ 3 V VCC 0.25 VCCIOH(max) = -6 mA 13/ VCC 0.6 VCCLow-level output voltage VOLIOL(max) = 1.5 mA 12/ -40C to 105C 2.2 V VSSVSS+ 0.25 V IOL(max) = 6 mA 13/ VSSVSS+ 0.6 IOL(max) = 1.5 mA 12/ 3 V VSSVSS+ 0.25 IOL(max) = 6 mA 13/ VSSVSS+
39、0.6 Output frequency - ports P1 through P8 Port output frequency with load fPx.yP1.4/SMCLK, CL= 20 pF, RL= 1 k 14/ 15/ -40C to 105C 2.2 V dc 10 MHz 3 V dc 12 Clock output frequency fPort_CLKP2.0/ACLK/CA2, P1.4/SMCLK, CL = 20 pF 15/ -40C to 105C 2.2 V dc 12 MHz 3 V dc 16 Duty cycle of output frequenc
40、y t(Xdc)P5.6/ACLK, CL= 20 pF, LF mode -40C to 105C 30 70 % P5.6/ACLK, CL= 20 pF, XT1 mode 40 60 P5.4/MCLK, CL= 20 pF, XT1 mode 40 60 P5.4/MCLK, CL= 20 pF, DCO 50% - 15 ns 50% + 15 ns P1.4/SMCLK, CL= 20 pF, XT2 mode 40 60 % P1.4/SMCLK, CL= 20 pF, DCO 50% - 15 ns 50% + 15 ns POR/brownout reset (BOR) 1
41、6/ 17/ See figure 6 - 8. Operating voltage VCC(start)dVCC/dt 3 V/s -40C to 105C 0.7 x V(B_IT-) TYP V Negative going VCCreset threshold voltage V(B_IT-)dVCC/dt 3 V/s -40C to 105C 1.71 V VCCreset threshold hysteresis Vhys(B_IT-)dVCC/dt 3 V/s -40C to 105C 70 210 mV BOR reset release delay time td(BOR)-
42、40C to 105C 2000 s Pulse length at RST/NMI pin to accept a reset t(reset)-40C to 105C 2.2 V/ 3V 2 s See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16
43、236 DWG NO. V62/09620 REV PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max SVS (Supply voltage supervisor/monitor) t(SVSR)dVCC/dt 30 V/ms See figure 9. -40C to 105C 5 150 s dVCC/dt 30 V/ms 2000 td(SVSon
44、)SVSON, switch from VLD = 0 to VLD 0 -40C to 105C 3 V 20 150 s tsettleVLD 0 18/ -40C to 105C 12 s V(SVSstart)VLD 0, VCC/dt 3 V/s See figure 9. -40C to 105C 1.7 V Vhys(SVS_IT-)VCC/dt 3 V/s See figure 9. VLD = 1 -40C to 105C 70 210 mV VLD = 2 to 14 V(SVS_IT-)x 0.004 V(SVS_IT-)x 0.016 V VCC/dt 3 V/s Se
45、e figure 9. External voltage applied on A7. VLD = 15 4.4 20 mV V(SVS_IT-)VCC/dt 3 V/s See figure 9 and figure 10. VLD = 1 -40C to 105C 1.8 2.05 V VLD = 2 1.94 2.25 VLD = 3 2.05 2.37 VLD = 4 2.14 2.48 VLD = 5 2.24 2.6 VLD = 6 2.33 2.71 VLD = 7 2.46 2.86 VLD = 8 2.58 3 VLD = 9 2.69 3.13 VLD = 10 2.83
46、3.29 VLD = 11 2.94 3.42 VLD = 12 3.11 3.61 19/ VLD = 13 3.24 3.76 19/ VLD = 14 3.43 3.99 19/ VCC/dt 3 V/s See figure 9 and figure 10. External voltage applied on A7. VLD = 15 1.1 1.3 ICC(SVS)20/ VLD 0 -40C to 105C 2.2 V/ 3 V 15 A See footnotes at end of table. Provided by IHSNot for ResaleNo reprodu
47、ction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09620 REV PAGE 10 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/ unless otherwise specified TAVCCLimits Unit Min Max DCO frequency Supply voltage range VCCRSELx 100 kHz 0.6 Setup time for a repeated START tSU,STAfSCL 100 kHz 2.2 V/3 V 4.7 fSCL 100 kHz 0.6 Data hold time tHD,DAT2.2 V/3 V 0 ns Dat
