1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM
2、 DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL RECEIVER, MONOLITHIC SILICON 09-05-20 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09627 REV PAGE 1 OF 13 AMSC N/A 5962-V055-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH
3、S-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance digital receiver microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item
4、 Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09627 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2
5、.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TFP401A-EP Digital receiver 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 100 MS-026 Plastic Quad Flatpack 1.2.3 Lead finishes. The
6、 lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
7、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage, (DVDD, AVDD, OVDD, PVDD) -0.3 V to 4.0 V Input voltage, logic/analog signals . -0.3 V to 4.0 V Storage temperature range (TSTG) . -
8、65C to 150C 2/ Operating temperature range . -55C to 125C Case temperature for 10 s . 260C Lead temperature (1.6 mm (1/16 in) from the case for 10 s) . 260C Maximum package power dissipation: Soldered . 4.3 W 3/ Not soldered . 2.7 W 4/ ESD protection, all pins 25 kV, Human Body model JEDEC latch up
9、(EIA/JESD78) 100 mA 1.4 Recommended operating conditions. 5/ Supply voltage VDD, (DVDD, AVDD, PVDD, OVDD) . 3.0 V to 3.6 V Pixel time, (tpix) . 6.06 ns to 40 ns 6/ Single ended analog input termination resistance, . 45 to 75 Operating free air temperature, (TA) . -55C to 125C 1/ Stresses beyond thos
10、e listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rate
11、d conditions for extended periods may affect device reliability. 2/ Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 3/ Specified with the bond pad on the backside of the package soldered to a 2 oz. C
12、u plate PCB thermal plane. Specified at maximum allowed operating temperature, 70C. 4/ The bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70C. 5/ Use of this product beyond the manufacturers design rules or stated param
13、eters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ tpixis the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpixwhen in 1-pixel/clock mo
14、de and 2tpixwhen in 2-pixel/clock mode. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standa
15、rd Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer
16、s part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical
17、characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.
18、5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Function block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Timing diagram. The timing diagram shall be
19、as shown in figure 4-10. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Condition
20、s 2/ Limits Unit Min Max DC Specifications High level digital input voltage VIH2 DVDDV Low level digital input voltage VIL0 0.8 High level output drive current IOHST = High VOH= 2.4 V 5 16.3 mA ST = Low VOH= 2.4 V 3 10.3 Low level output drive current IOLST = High VOL= 0.8 V 8 19 ST = Low VOL= 0.8 V
21、 4 11 Hi-Z output leakage current IOZ PD = low or PDO = Low -1 1 A Analog input differential voltage 3/ VID75 1200 mV Analog input common mode voltage 3/ VICAVDD-300 AVDD-37 mV Open circuit analog input voltage VI(OC)AVDD-10 AVDD+10 mV Normal 2-pix/clock power supply current 4/ IDD(2PIX)ODCK = 82.5
22、MHz 2-pix/clock 370 mA Power down current 5/ IPDPD = low 10 mA Output drive power down current 5/ IPDOPDO = Low 35 TYP mA AC Specifications Differential input sensitivity 6/ VID7/ 150 1560 mVp-p Analog input intra pair (+ to -) differential skew 7/ tps0.4 tbit8/ Analog input inter pair or channel to
23、 channel skew 7/ tccs1 tpix9/ Worse case differential input clock jitter tolerance 10/ 7/ 11/ tijit50 ps Fall time of data and control signals 12/ 13/ 11/ tf1ST = Low, CL = 5 pF 2.4 ns ST = High, CL = 10 pF 1.9 Rise time of data and control signals 12/ 13/ 11/ tr1ST = Low, CL = 5 pF 2.4 ST = High, C
24、L = 10 pF 1.9 Rise time of ODCK clock 11/ 12/ tr2ST = Low, CL = 5 pF 2.4 ST = High, CL = 10 pF 1.9 Fall time of ODCK clock 11/ 12/ tf2ST = Low, CL = 5 pF 2.4 ST = High, CL = 10 pF 1.9 Setup time, data and control signal to falling edge of ODCK 11/ tsu11 pixel/clock, PIXS = low, OCK_INV = low 1.8 2 p
25、ixel/clock, PIXS = high, STAG = high, OCK_INV = low 3.8 2 pixel and STAG , PIXS = high, STAG = low, OCK_INV = low 0.6 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A
26、 CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 6 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 2/ Limits Unit Min Max AC Specifications Hold time, data and control signal to falling edge of ODCK 11/ th11 pixel/clock, PIXS = low, OCK_INV = low 0.6 ns 2 pixel and
27、STAG , PIXS = high, STAG = low, OCK_INV = low 2.5 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = low 2.9 Setup time, data and control signal to rising edge of ODCK 11/ tsu21 pixel/clock, PIXS = low, OCK_INV = high 2.1 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 4 2 pixel and STAG , P
28、IXS = high, STAG = low, OCK_INV = high 1.5 Hold time, data and control signal to rising edge of ODCK 11/ th21 pixel/clock, PIXS = low, OCK_INV = high 0.3 2 pixel and STAG , PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 2.1 ODCK frequency fODCKPIX
29、 = low (1-PIX/CLK) 25 165 MHz PIX = High (2-PIX/CLK) 12.5 82.5 ODCK duty-cycle 45% 75% Propagation delay time from PD low to Hi-Z outputs 11/ tpd(PDL)9 ns 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperat
30、ure range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Over operating free air temperature range, (unless
31、otherwise noted). 3/ Specified as dc characteristic with no overshoot or undershoot. 4/ Alternating 2-pixel black/2-pixel white patter. ST = high, STAG = high, QE23:0 and QO23:0 CL = 10 pF. 5/ Analog inputs are open circuit (transmitter is disconnected from (TFP401A). 6/ Specified as ac parameter to
32、 include sensitivity to overshoot, undershoot and reflection. 7/ By characterization. 8/ tbitis 1/10 the pixel time, tpix. 9/ tpixis the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpixin 1-pixel/clock mode or 2tpixwhen in 2-pixel/clock mode. 10/ Measured
33、differentially at 50% crossing using ODCK output clock as trigger. 11/ Not production test. 12/ Rise and fall time measured as time between 20% and 80% of signal amplitude. 13/ Data and control signals are: QE23:0, QO23:0, DE, HSYNC, VSYNC and CTL3:1. Provided by IHSNot for ResaleNo reproduction or
34、networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 7 Case X Dimension Symbol Millimeters Symbol Millimeters Min Max Min Max A 1.20 D/E 15.80 16.20 A1 0.95 1.05 D1/E1 13.80 14.20 A2 0.25 Typ D2/E2 12.
35、00 Typ A3 0.05 0.15 e 0.50 NOM b 0.17 0.27 L1 0.45 0.75 c 0.13 NOM NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion. 4. This package is designed to be soldered to a thermal pad on the b
36、oard. Refer to the manufacturer data for information regarding recommended board layout. 5. Falls within JEDEC MS-026. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE
37、IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 8 Case X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 DFO 26 QE14 51 QO2 76 OGND 2 PD 27 QE15 52 QO3 77 QO23 3 ST 28 OGND 53 QO4 78 OVDD 4 PIXS 29 OVDD 54 QO5 79 AGND 5 GND
38、 30 QE16 55 QO6 80 Rx2+ 6 DVDD 31 QE17 56 QO7 81 Rx2- 7 STAG 32 QE18 57 OVDD 82 AVDD 8 SCDT 33 QE19 58 OGND 83 AGND 9 PDO 34 QE20 59 QO8 84 AVDD 10 QE0 35 QE21 60 QO9 85 Rx1+ 11 QE1 36 QE22 61 QO10 86 Rx1- 12 QE2 37 QE23 62 QO11 87 AGND 13 QE3 38 DVDD 63 QO12 88 AVDD 14 QE4 39 GND 64 QO13 89 AGND 15
39、 QE5 40 CTL1 65 QO14 90 Rx0+ 16 QE6 41 CTL2 66 QO15 91 Rx0- 17 QE7 42 CTL3 67 DVDD 92 AGND 18 OVDD 43 OVDD 68 GND 93 RxC+ 19 OGND 44 ODCK 69 QO16 94 RxC- 20 QE8 45 OGND 70 QO17 95 AVDD 21 QE9 46 DE 71 QO18 96 EXT RES 22 QE10 47 VSYNC 72 QO19 97 PVDD 23 QE11 48 HSYNC 73 QO20 98 PGND 24 QE12 49 QO0 74
40、 QO21 99 RSVD 25 QE13 50 QO1 75 QO22 100 OCK_INV FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 9 FIGURE 3. Functio
41、nal block diagram. FIGURE 4. Timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 10 FIGURE 5. Timing diagram. FIGURE 6. Timing diagram.
42、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 11 FIGURE 7. Timing diagram. FIGURE 8. Timing diagram. Provided by IHSNot for ResaleNo reproduction
43、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 12 FIGURE 9 Timing diagram. FIGURE 10 Timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
44、HS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09627 REV PAGE 13 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such p
45、rocedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers s
46、tandard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufact
47、urers data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor par
