1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device types 02 and 03. Add three footnotes under paragraph 1.2.1. Add footnote under paragraph 6.3. - ro 10-01-21 C. SAFFLE Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A A PAGE 18 19 20 21 22 23 REV STATUS OF PAGES RE
2、V A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL-LINEAR, LOW POWER, 8-CHANNEL, SERIAL
3、10 BIT ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON 09-09-01 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/09628 REV A PAGE 1 OF 23 AMSC N/A 5962-V018-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTE
4、R, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a low power 8-channel, serial, 10 bit analog to digital converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendo
5、r Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/09628 - 01 X B Drawing Device type Case outline Lead finish number (S
6、ee 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 1/ MAX149BMAP/PR Low power 8-channel, serial, 10 bit analog to digital converter 02 2/ MAX149BMAP/PR2 Low power 8-channel, serial, 10 bit analog to digital converter 03 3/ MAX149BMAP/PR3 Low power 8-chann
7、el, serial, 10 bit analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 20 MO-150 Shrink small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provide
8、d by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other _ 1/ Device type 01, 100% burn-in and 100% testing at room, hot, and cold temperatures. 2/ Device type 02, 100% testing at room, hot, and cold temperatures.
9、3/ Device type 03, 100% testing at room temperature only, guaranteed by design to the limits specified in table I for hot and cold temperatures. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A COD
10、E IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 3 1.3 Absolute maximum ratings. 4/ VDDto AGND, DGND -0.3 V to +6 V AGND to DGND . -0.3 V to +0.3 V CH0 CH7, COM to AGND, DGND . -0.3 V to (VDD+ 0.3 V) VREF, REFADJ to AGND -0.3 V to (VDD+ 0.3 V) Digital inputs to DGND . -0.3 V to +6 V Digital outputs to
11、 DGND . -0.3 V to (VDD+ 0.3 V) Digital output sink current . 25 mA Storage temperature range (TSTG) -60C to +150C Lead temperature (soldering, 10 seconds) . +300C Junction temperature range (TJ) +150C Electrostatic discharge (ESD): Human body model (HBM) . 800 V Moisture sensitivity level (MSL) Leve
12、l 1 1.4 Recommended operating conditions. 5/ Operating free-air temperature range (TA) . -55C to +125C 1.5 Thermal data table. Case outline letter X X Unit PC board Single layer Multi-layer 6/ Power dissipation (PD), maximum at +70C 640 952 mW Power dissipation (PD) derating above +70C 8.0 11.9 mW/C
13、 Thermal resistance, junction to case (JC) 33 32 C/W Thermal resistance, junction to ambient (JA) 125 84 C/W 4/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
14、 other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users r
15、isk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. 6/ Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal c
16、onsiderations, refer to www.maxim- Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard
17、Outlines for Semiconductor Devices JEDEC JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3.
18、REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked wit
19、h the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension
20、. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth tables. The truth tables shall be a
21、s shown in figure 3. 3.5.4 Block diagram. The block diagram shall be as shown in figure 4. 3.5.5 Load circuits. The load circuits shall be as shown in figures 5 and 6. 3.5.6 Timing waveforms. The timing waveforms shall be as shown in figure 7. Provided by IHSNot for ResaleNo reproduction or networki
22、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max DC accuracy 3/ Resolution -
23、55C to +125C 01,02,03 10 Bits Relative accuracy 4/ INL -55C to +125C 01,02,03 1.0 LSB Differential nonlinearity DNL No missing codes over temperature -55C to +125C 01,02,03 1 LSB Offset error OE -55C to +125C 01,02,03 2 LSB Gain error 5/ AE -55C to +125C 01,02,03 2 LSB Gain temperature coefficient A
24、E/T -55C to +125C 01,02,03 0.25 typical ppm / C Channel to channel offset matching -55C to +125C 01,02,03 0.05 typical LSB Dynamic specifications 6/ Signal to noise + distortion noise SINAD -55C to +125C 01,02,03 66 typical dB Total harmonic distortion THD Up to the fifth harmonic -55C to +125C 01,0
25、2,03 -70 typical dB Spuriuos-free dynamic range SFDR -55C to +125C 01,02,03 70 typical dB Channel to channel crosstalk 65 kHz, 2.500 VP-P7/ -55C to +125C 01,02,03 -75 typical dB Small signal bandwidth SSBW -3 dB rolloff -55C to +125C 01,02,03 2.25 typical MHz Full power bandwidth FPBW -55C to +125C
26、01,02,03 1.0 typical MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 6 TABLE I. Electrical performance characte
27、ristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Conversion rate See figure 7 Conversion time 8/ tCONVInternal clock, SHDN = unconnected -55C to +125C 01,02,03 5.5 7.5 s Internal clock, SHDN = VDD35 65 External clock = 2 MHz, 12 clocks/conversion 6 Track
28、/hold acquisition time tACQ-55C to +125C 01,02,03 1.5 s Aperture delay -55C to +125C 01,02,03 30 typical ns Aperture jitter -55C to +125C 01,02,03 50 typical ps Internal clock frequency fCLKISHDN = unconnected -55C to +125C 01,02, 1.8 typical MHz SHDN = VDD03 0.225 typical External clock frequency f
29、CLKE-55C to +125C 01,02, 0.1 2.0 MHz Data transfer only 03 0 2.0 Analog/com inputs Input voltage range, 9/ single ended and differential VINUnipolar, COM = 0 V -55C to +125C 01,02,03 0 to VREFV Bipolar, COM = VREF/2 VREF/2 Multiplexer leakage current ILOn/off leakage current, VCH_= 0 V or VDD-55C to
30、 +125C 01,02,03 1 A Input capacitance CIN-55C to +125C 01,02,03 16 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628
31、REV A PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Internal reference (Reference buffer enabled) VREFoutput voltage VOUT10/ +25C 01,02,03 2.470 2.530 V VREFshort circuit current IOS-55C to +125C 01,02,03
32、 30 mA VREFtemperature coefficient -55C to +125C 01,02,03 30 typical ppm/ C Load regulation 11/ LD 0 to 0.2 mA output load -55C to +125C 01,02,03 0.35 typical mV Capacitive bypass at VREFCBPVInternal compensation mode -55C to +125C 01,02, 0 F External compensation mode 03 4.7 Capacitive bypass at RE
33、FADJ CBPR-55C to +125C 01,02,03 0.01 F REFADJ adjustment range -55C to +125C 01,02,03 1.5 typical % External reference at VREF(Buffer disabled) VREFinput 12/ voltage range VIN-55C to +125C 01,02,03 1.0 VDD+ 50 mV V VREFinput current IINVREF= 2.500 V -55C to +125C 01,02,03 150 A VREFinput resistance
34、RIN-55C to +125C 01,02,03 18 k Shutdown VREFinput current INSD-55C to +125C 01,02,03 10 A REFADJ buffer disable threshold VBDT-55C to +125C 01,02,03 VDD 0.5 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPP
35、LY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 8 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max External reference at REFADJ Capacitive bypass at VREFCBPVInternal comp
36、ensation mode -55C to +125C 01,02, 0 F External compensation mode 03 4.7 Reference buffer gain ARB -55C to +125C 01,02,03 2.06 typical V/V REFADJ input current IIN-55C to +125C 01,02,03 50 A Digital inputs ( DIN, SCLK, CS , SHDN ) DIN, SCLK, CS , input high voltage VIHVDD 3.6 V -55C to +125C 01,02,
37、2.0 V VDD 3.6 V 03 3.0 DIN, SCLK, CS , input low voltage VIL-55C to +125C 01,02,03 0.8 V DIN, SCLK, CS , input hysteresis VHYST-55C to +125C 01,02,03 0.2 typical V DIN, SCLK, CS , input leakage VINVIN= 0 or VDD-55C to +125C 01,02,03 1 A DIN, SCLK, CS , input capacitance CIN13/ -55C to +125C 01,02,03
38、 15 pF SHDNinput high voltage VSH-55C to +125C 01,02,03 VDD 0.4 V SHDNinput mid voltage VSM-55C to +125C 01,02,03 1.1 VDD 1.1 V SHDNinput low voltage VSL-55C to +125C 01,02,03 0.4 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
39、om IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 9 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Digital inputs continued. ( DIN, SCLK, CS , SHDN
40、 ) SHDN input current ISSHDN = 0 or VDD-55C to +125C 01,02,03 4.0 A SHDN voltage, unconnected VFLTSHDN = unconnected -55C to +125C 01,02,03 VDD/2 typical SHDN maximum allowed leakage, mid point ILMPSHDN = unconnected -55C to +125C 01,02,03 100 nA Digital outputs (DOUT, SSTRB) Output voltage low VOLI
41、SINK= 5 mA -55C to +125C 01,02, 0.4 V ISINK= 16 mA 03 0.8 Output voltage high VOHISOURCE= 0.5 mA -55C to +125C 01,02,03 VDD 0.5 V Three-state leakage current ILCS = VDD-55C to +125C 01,02,03 10 A Three-state output capacitance COUTCS = VDD13/ -55C to +125C 01,02,03 15 pF Power requirements Positive
42、supply voltage VDD-55C to +125C 01,02,03 2.70 5.25 V Positive supply current IDDVDD= 5.25 V, operating mode, full scale input -55C to +125C 01,02,03 3.0 mA VDD= 3.6 V, operating mode, full scale input 2.0 VDD= 5.25 V, full power down 15 A VDD= 3.6 V, full power down 10 Fast power down 70 Power suppl
43、y 14/ rejection PSR Full scale input, external reference = 2.500 V, VDD= 2.7 V to 5.25 V -55C to +125C 01,02,03 0.3 typical mV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OH
44、IO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 10 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Timing characteristics See figure 7 Acquisition time tACQ-55C to +125C 01,02,03 1.5 s DIN to SCLK setu
45、p tDS-55C to +125C 01,02,03 100 ns DIN to SCLK hold tDH-55C to +125C 01,02,03 0 ns SCLK fall to output data valid tDOSee figure 5 -55C to +125C 01,02,03 20 240 ns CS fall to output enable tDVSee figure 5 -55C to +125C 01,02,03 240 ns CS rise to output disable tTRSee figure 6 -55C to +125C 01,02,03 2
46、40 ns CS to SCLK rise setup tCSS -55C to +125C 01,02,03 100 ns CS to SCLK rise hold tCSH -55C to +125C 01,02,03 0 ns SCLK pulse width high tCH-55C to +125C 01,02,03 200 ns SCLK pulse width low tCL-55C to +125C 01,02,03 200 ns SCLK fall to SSTRB tSSTRBSee figure 5 -55C to +125C 01,02,03 240 ns See fo
47、otnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/09628 REV A PAGE 11 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions 2/Temperature, TA Device type Limits Unit Min Max Timing characteristics continued. See figure 7 CS fall to SST
