1、 REVISIONSLTR DESCRIPTION DATE APPROVEDPrepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Original date of drawing YY MM DD CHECKED BY Ph
2、u H. Nguyen TITLE MICROCIRCUIT, DIGITAL, PLL FREQUENCY SYNTHESIZER, MONOLITHIC SILICON 11-01-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/11606 REV PAGE 1 OF 11 AMSC N/A 5962-V027-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
3、HS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance PLL frequency synthesizer microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item
4、 Drawing Administrative Control Number. The manufacturer,s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/11606 - 01 X B Drawing Device type Case outline Lead finish number (See 1.
5、2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 ADF4106-EP PLL frequency synthesizer 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Lead Thin Shrink Small Outline
6、Package Y 20 JEDEC MO-220 Lead Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other
7、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Voltage referenced : AVDDto GND 2/ . -0.3 V to +7.0 V AVDDto DVDD. -0.3 V t
8、o +0.3 V VPto GND -0.3 V to +5.8 V VPto AVDD-0.3 V to +5.8 V Digital I/O voltage to GND . -0.3 V to VDD+ 0.3 V Analog I/O voltage to GND -0.3 V to VP+ 0.3 V REFIN, RFINA, REFINB to GND -0.3 V to VDD + 0.3 V Ambient operating temperature range . -55C to +125C Storage temperature range . -65C to +150C
9、 Maximum junction temperature (TJ) 150C Thermal impedance,( JA): Case outline X 112C /W Case outline Y (Paddle soldered) 30.4C /W Reflow soldering: Peak temperature 260C Time at peak temperature 40 sec Transistor count: CMOS 6425 Bipolar 303 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standa
10、rd Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 3103 North 10thSt., Suite 240-S, Arlington, VA 22201-2107or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the man
11、ufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 El
12、ectrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
13、only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2/ GND = AGND = DGND = 0 V. Provided by IHSN
14、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
15、 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Timing diagrams. The timi
16、ng diagrams shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol T
17、est conditions 2/ unless otherwise specified Limits Unit Min Max RF characteristics RF Input frequency RFINFor lower frequency, ensure slew rate (SR) 320/s 0.5 6.0 GHz RF input sensitivity -10 0 dBm Maximum allowable prescaler output frequency 3/ P = 8 300 MHz P = 10 325 MHz REFINcharacteristics REF
18、INinput frequency For f 50 V/s 20 300 MHz REFINinput sensitivity 4/ Biased at AVDD/240.8 VDDVp-p REFINinput capacitance 10 pF REFINinput current 100 A Phase detector Phase detector frequency 6/ ABP = 0, 0 (2.9 ns antibacklash pulse width) 104 MHz Charge pump Sink/Source High value Low value Absolute
19、 accuracy RSETrange ICPWith RSET= 5.1 k 5 TYP mA 625 TYP A With RSET= 5.1 k 2.5 TY % 3.0 11 k Three stage leakage ICP1 nA typical; TA= 25C 2 nA Sink and source current matching 0.5 VCP VP 0.5 V 2 TYP % ICPvs VCP VCP VP 0.5 V 1.5 TYP % ICPvs temperature VCP= VP/2 2 TYPLogic inputs Input high voltage
20、VIH1.4 V Input low voltage VIL0.6 Input current IINH, IINL1 A Input capacitance CIN10 pF Logic outputs Output high voltage VOHOpen-drain output chosen, 1 k pull up resistor to 1.8 V CMOS output chosen 1.4 V VDD 0.4 Output high current IOH100 A Output low voltage VOLIOL= 500 A 0.4 V Power supplies AV
21、DD2.7 3.3DVDDAVDDV VPAVDD VP 5.5 V AVDD5.5 V IDD(AIDD+DIDD) 7/ 9.0 mA TYP 11 mA IDD(AIDD+DIDD) 8 9.5 T 11.5IDD(AIDD+DIDD) 9/ 10.5 mA TYP 13 IPTA= 25C 0.4Power down mode (AIDD+ DIDD) 10/ 10 TYP A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted witho
22、ut license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions 2/ unless otherwise specified Limits Unit Min Max Noise characteristics Normalized phase nois
23、e floor (PNSYNTH) 11/ PLL loop BW = 500 kHz -223 TYP dBc/Hz Normalized 1/f Noise (PN1_f) 12/ Measured at 10 kHz offset, normalized to 1 GHz VCO output -122 TYP Phase noise performance 13/ 900 MHz 14/ 5800 MHz 15/ 5800 MHz 16/ dBc 1 kHz offset and 200 kHz PFD frequency -92.5 TYP 1 kHz offset and 200
24、kHz PFD frequency -76.5 TYP 1 kHz offset and 1 MHz PFD frequency -83.5 TYP Spurious signals 900 MHz 14/ 5800 MHz 15/ 5800 MHz 16/ dBc 200 kHz/400 kHz and 200 kHz PDF frequency -90 -92 200 kHz/400 kHz and 200 kHz PDF frequency -65 -70 1 MHz/2 MHz and 1 MHz PDF frequency -70 -75 Timing characteristics
25、 17/ Data to clock setup time t110 ns Data to clock hold time t210 Clock high duration t325 Clock low duration t425 Clock to LE setup time t510 LE pulse width t620 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified
26、 temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ AVDD= DVDD= 3 V 10%, AVDD VP 5.5 V, AGND =
27、 DGND = CPGND = 0 V, RSET= 5.1 k, dBm referred to 50 , -55C TA +125C, unless otherwise noted. 3/ This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensutr that the RF input is divided down to a frequency that is less than this value. 4/ AVDD= DVDD=
28、3.0 V. 5/ AC coupling ensures AVDD/2 bias. 6/ Guaranteed by design. Sample tested to ensure compliance. 7/ TA= 25C; AVDD= DVDD= 3 V; P = 16; RFIN= 900 MHz. 8/ TA= 25C; AVDD= DVDD= 3 V; P = 16; RFIN= 2.0 GHz. 9/ TA= 25C; AVDD= DVDD= 3 V; P = 32; RFIN= 6.0 GHz. 10/ TA= 25C; AVDD= DVDD= 3.3 V; R = 1638
29、3; A = 63; B = 891; P = 32; RFIN= 6.0 GHz. 11/ The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYTH= PNTOT 10 log FPFD 20 log N. 12/ The PLL phase noise is compos
30、ed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and ficker noise are modeled
31、in ADIsimPLL. 13/ The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFINfor the synthesizer (fREFOUT= 10 MHz 0 dBm). 14/ fREFIN= 10 MHz, fPFD= 200 kHz; offset frequency = 1 kHz, fRF= 900 MHz; N = 4500;
32、 loop B/W = 20 kHz. 15/ fREFIN= 10 MHz, fPFD= 200 kHz; offset frequency = 1 kHz, fRF= 5800 MHz; N = 29,000; loop B/W = 20 kHz. 16/ fREFIN= 10 MHz, fPFD= 1 MHz; offset frequency = 1 kHz, fRF= 5800 MHz; N = 5800; loop B/W = 100 kHz. 17/ AVDD= DVDD= 3 V 10%, AVDD VP 5.5 V, AGND = DGND = CPGND = 0 V, RS
33、ET= 5.1 k, dBm referred to 50 , -40C TA +85C, unless otherwise noted. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 7 Case X Dimensions Symbol Millimeters S
34、ymbol Millimeters Min Max Min Max A 1.20 E 4.30 4.50 A1 0.05 0.15 E1 6.40 TYP b 0.19 0.30 e 0.65 BSC c 0.09 0.20 L 0.45 0.75 D 4.90 5.10 FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE
35、 A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 8 Case Y Dimensions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.80 1.00 D1/E1 3.75 BSC A1 0.80 e 0.50 BSC A2 0.20 REF e1 1.95 2.25A3 0.05 e2 0.25 b 0.18 0.30 L 0.50 0.75 D/E 4.00 BSC L1 0.60 FIGURE 1. Case outline - Continued. Provided
36、 by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 9 Case X Case Y Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 RSET9 DGND 1 CPGND 11 CE 2 CP 10
37、 CE 2 AGND 12 CLK 3 CPGND 11 CLK 3 AGND 13 DATA 4 AGND 12 DATA 4 RFINB 14 LE 5 RFINB 13 LE 5 RFINA 15 MUXOUT 6 RFINA 14 MUXOUT 6 AVDD16 DVDD7 AVDD15 DVDD7 AVDD17 DVDD8 REFIN16 VP8 REFIN18 VP9 DGND 19 RSET10 DGND 20 CP FIGURE 2. Terminal connections. Case X Case Y Pin Name Description PinNo. Pin No.
38、1 19 RSETConnecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSETpin is 0.66 V. The relationship between ICPand RSETis: ICP MAX = nullnull.nullRSETSo, with RSET= 5.1 k, ICPMAX= 5 mA. 2 20 CP Charge Pump Output. When enabl
39、ed, this provides ICPto the external loop filter, which in turn drives the external VCO. 3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB Complementary Input to the RF Prescaler. Th
40、is point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. 6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. 7 6, 7 AVDDAnalog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog grou
41、nd plane should be placed as close as possible to this pin. AVDDmust be the same value as DVDD. 8 8 REFINReference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator or it can be
42、ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2. 11 12 CLK Serial Clock Input. This serial
43、clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
44、a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches with the latch being selected using the control bits. 14 15 MUXOUT The multiplexer output allows either the lock detect, the scaled RF, or t
45、he scaled reference frequency to be accessed externally. 15 16, 17 DVDDDigital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDDmust be the same value as AVDD. 16 18 VPCharge Pump Power Supply.
46、This should be greater than or equal to VDD. In systems where VDDis 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V. EP Exposed Pad. The exposed pad must be connected to AGND. FIGURE 3. Pin Function Descriptions. Provided by IHSNot for ResaleNo reproduction or ne
47、tworking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 10 FIGURE 3. Functional block diagram. FIGURE 4. Timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/11606 REV PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures
