1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Phu H. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ O
2、riginal date of drawing YY MM DD CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL-LINEAR, QUAD, 14-BIT, 125 MSPS SERIAL LVDS 1.8 V ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON 13-09-19 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/13627 REV PAGE 1 OF 14 AMSC N/A 5962-V08
3、5-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance quad, 14-bit,
4、 125 MSPS serial LVDS 1.8 V analog-to-digital converter microcircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number
5、 for identifying the item on the engineering documentation: V62/13627 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 AD9253-EP Quad, 14-bit, 125 MSPS serial LVDS 1.8 V analog-to-digital co
6、nverter 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC MO-220-WKKD Lead Lead Frame Chip Scale Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device
7、manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO
8、. V62/13627 REV PAGE 3 1.3 Absolute maximum ratings. 1/ AVDD to AGND -0.3 V to +2.0 V DRVDD to AGND . -0.3 V to +2.0 V Digital outputs (D0x, D1x, DCO+, DCO-, FCO+, FCO-) to AGND -0.3 V to +2.0 V CLK+, CLK- to AGND . -0.3 V to +2.0 V VIN+x, VIN-x to AGND . -0.3 V to +2.0 V SCLK/DTP, SDIO/OLM, CSB to
9、AGND . -0.3 V to +2.0 V SYNC, PDWN to AGND . -0.3 V to +2.0 V RBIAS to AGND . -0.3 V to +2.0 V VREF, SENSE to AGND -0.3 V to +2.0 V Operating temperature range (Ambient) -55C to +125C Maximum junction temperature 150C Lead temperature (Soldering, 10 sec) 300C Storage temperature range (Ambient) -65C
10、 to 150C 1.5 Thermal characteristics. Thermal resistance Case outline Air flow velocity (m/sec) JA 2/ JTJBJCTOP JCBOTTOM Unit Case X 0.0 1.0 2.5 20.3 17.6 16.5 0.10 0.16 0.20 5.9 N/A 3/ N/A 3/ 6.1 N/A 3/ N/A 3/ 1.0 N/A 3/ N/A 3/ C/W C/W C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCI
11、ATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 1/ Stresses above those listed under
12、“Absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those beyond indicated in the operational section of this specifications is not implied. Exposure to absolute maximum rate
13、d conditions for extended periods may affect device reliability. 2/ JAfor a 4-layer printed circuit board (PCB) with solid ground plane (simulated). Exposed pad soldered to PCB. 3/ N/A = not applicable. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,
14、-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 ident
15、ifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics
16、are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The t
17、erminal connections shall be as shown in figure 2. 3.5.3 Terminal function description. The Terminal function description shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or network
18、ing permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test 2/ Test conditions 3/ Temp Limits Unit Min Typ Max DC SPECIFICATIONS Resolution 14 Bits Accuracy No missin
19、g codes Full Guaranteed Offset error Full -0.8 -0.3 +0.1 % FSR Offset matching Full -0.6 +0.2 +0.6 % FSR Gain error Full -12 -3 +2 % FSR Gain matching Full 1.1 1.6 % FSR Differential Nonlinearity (DNL) Full 25C -0.8 0.8 +1.9 LSB LSB Integral Nonlinearity (INL) Full 25C -4.5 2.0 +4.5 LSB LSB Temperat
20、ure drift Offset error Full 2 ppm/C Gain error Full 50 ppm/C Internal voltage reference Output voltage (1 V Mode) Full 0.98 1.0 1.02 V Load regulation at 1.0 mA (VREF= 1 V) Full 2 mV Input resistance Full 7.5 k Input referred noise VREF= 1.0 V 25C 0.94 LSB rms Analog inputs Differential input voltag
21、e (VREF= 1 V) Full 2 V p-p Common mode voltage Full 0.9 V Differential input resistance 5.2 k Differential input capacitance Full 3.5 pF Power supply AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD4/ Full 183 205 mA IDRVDD(ANSI-644 mode) 4/ Full 61 63 mA IDRVDD(Reduce range mode) 4/ 25C 53 mA
22、 Total power consumption DC input Full 403 mW Sine wave input (Four channels including output drivers ANSI 644 mode) Full 440 480 mW Sine wave input (Four channels including output drivers reduced range mode) 25C 425 mW Power down mode Full 2 mW Standby mode 5/ Full 235 mW See footnote at end of tab
23、le. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test 2/ Test conditions 3/ Temp Limits U
24、nit Min Typ Max AC SPECIFICATIONS Signal to Noise Ratio (SNR) fIN= 9.7 MHz 25C 75.3 dBFS fIN= 30.5 MHz 25C 75.2 fIN= 70 MHz Full 72 74.1 fIN= 140 MHz 25C 72.2 fIN= 200 MHz 25C 70.7 Signal to Noise And Distortion ratio (SINAD) fIN= 9.7 MHz 25C 75.2 dBFS fIN= 30.5 MHz 25C 75.1 fIN= 70 MHz Full 71.7 74
25、.0 fIN= 140 MHz 25C 71.9 fIN= 200 MHz 25C 70.4 Effective Number Of Bits (ENOB) fIN= 9.7 MHz 25C 12.2 Bits fIN= 30.5 MHz 25C 12.2 fIN= 70 MHz Full 12.0 fIN= 140 MHz 25C 11.7 fIN= 200 MHz 25C 11.4 Spurious Free Dynamic Range (SFDR) fIN= 9.7 MHz 25C 98 dBc fIN= 30.5 MHz 25C 92 fIN= 70 MHz Full 76 90 fI
26、N= 140 MHz 25C 85 fIN= 200 MHz 25C 83 Worst Harmonic (Second or Third) fIN= 9.7 MHz 25C -98 dBc fIN= 30.5 MHz 25C -92 fIN= 70 MHz Full -90 -76 fIN= 140 MHz 25C -85 fIN= 200 MHz 25C -83 Worst other Harmonic (Excluding Second or Third) fIN= 9.7 MHz 25C -101 dBFS fIN= 30.5 MHz 25C -100 fIN= 70 MHz Full
27、 -95 -83 fIN= 140 MHz 25C -96 fIN= 200 MHz 25C -92 Two tone Intermodulation Distortion (IMD) AN1 and AND2 = -7.0 dBFS fIN1= 70.5 MHz, fIN2= 72.5 MHz 25C 86 dBc Crosstalk 6/ Full -95 dB Crosstalk (Overrange condition) 7/ 25C -89 dB Power Supply Rejection Ratio (SPRR) 8/ AVDD 25C 48 dB DRVDD 25C 75 dB
28、 Analog input bandwidth, Full power 25C 650 MHz See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 7 TABLE I. Electrical performanc
29、e characteristics - Continued. 1/ Test 2/ Test conditions 3/ Temp Limits Unit Min Typ Max DIGITAL SPECIFICATIONS Clock inputs (CLK+, CLK-) Logic compliance CMOS/LVDS/LVPECL Differential input voltage 9/ Full 0.2 3.6 V p-p Input voltage range Full AGND 0.2 AGND + 0.2 V Input common mode voltage Full
30、0.9 V Input resistance (Differential) 25C 15 k Input capacitance 25C 4 pF Logic inputs (PDWN, SYNC, SCLK) Logic 1 voltage Full 1.2 AVDD + 0.2 V Logic 0 voltage Full 0 0.8 V Input resistance 25C 30 k Input capacitance 25C 2 pF Logic input (CSB) Logic 1 voltage Full 1.2 AVDD + 0.2 V Logic 0 voltage Fu
31、ll 0 0.8 V Input resistance 25C 26 k Input capacitance 25C 2 pF Logic input (SDIO/OLM) Logic 1 voltage Full 1.2 AVDD + 0.2 V Logic 0 voltage Full 0 0.8 V Input resistance 25C 26 k Input capacitance 25C 5 pF Logic output (SDIO/OLM) 10/ Logic 1 voltage (IOH= 800 A) Full 1.79 V Logic 0 voltage (IOL = 5
32、0 A) Full 0.05 V Digital outputs (D0x, D1x), ANSI-644 Logic compliance LVDS Differential output voltage (VOD) Full 290 345 400 mV Output offset voltage (VOS) Full 1.15 1.25 1.35 V Output coding (Default) Twos complement Digital outputs (D0x, D1x), low power, reduced signal option Logic compliance LV
33、DS Differential output voltage (VOD) Full 160 200 230 mV Output offset voltage (VOS) Full 1.15 1.25 1.35 V Output coding (Default) Twos complement See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COL
34、UMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test 2/ 11/ Test conditions 3/ Temp Limits Unit Min Typ Max SWITCHING SPECIFICATIONS Clock Input clock rate Full 10 1000 MHz Conversion rate Full 10 125 MSPS Clock Pul
35、se Width High (tEH) Full 4.00 ns Clock Pulse Width Low (tEL) Full 4.00 ns Output parameters 12/ Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD) 13/ Full t
36、FCO+ (tSAMPLE/16) ns DCO-to-Data Delay (tDATA) 13/ Full (tSAMPLE/16) - 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ops DCO-to-FCO Delay (tFRAME) 13/Full (tSAMPLE/16) - 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX tDATA-MIN) Full 50 200 ps Wake-Up Time (Standby)
37、25C 250 ns Wake-Up Time (Power-Down) 14/ 25C 375 s Pipeline Latency Full 16 Clock cycles Aperture Aperture Delay (tA) 25C 1 ns Aperture Uncertainty (Jitter, tJ) 25C 135 fs ms Out-of-Range Recovery Time 25C 1 Clock cycles See footnote at end of table. Provided by IHSNot for ResaleNo reproduction or n
38、etworking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ 1/ Testing and other quality control techniques are used to the extent deemed necessary to as
39、sure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/
40、 See the AN-835 manufacturers application note. Understanding high speed ADC testing and evaluation, for definitions and for details on how these tests were completed. 3/ AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -1.0 dBFS, unless otherwise noted. 4/ Me
41、asured with a low input frequency, full scale sine wave of all four channels. 5/ It can be controlled via the SPI. 6/ Crosstalk is measured at 70 MHz with an 1.0 dBFS analog input on one channel and no input on the adjacent channel. 7/ The over range condition is specified with 3 dB of the full-scal
42、e input range. 8/ PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. 9/ This is specified for LVDS and LVPECL
43、only. 10/ This is specified for 13 SDIO/OLM pins sharing the same connection. 11/ Measured on standard FR-4 material. 12/ Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 13/ tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE= 1/fS. 14/ Wak
44、e-up time is defined as the time required to return to normal operation from power-down mode. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 10 Case X Dimens
45、ions Symbol Millimeters Symbol Millimeters Min Max Min Max A 0.70 0.80 D1/E1 5.55 5.65 A1 0.05 e 0.50 BSC A2 0.20 REF S 0.35 0.45 b 0.18 0.30 S1 0.20 D/E 6.90 7.10 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC STANDARDS MO-220-WKKD. FIGURE 1. Case outline. D/E148PIN 1 ARE
46、AA1A2SEATINGPLANED1/E1b48 PLSSe1 12132425363748EXPOSED PADPIN 1INDICATORBOTTOM VIEWTOP VIEWS1A0.08Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/13627 REV PAGE 11 Case outl
47、ine X Terminal number Terminal symbol Terminal number Terminal symbol 1 VIN+D 48 VIN+C 2 VIN-D 47 VIN-C 3 AVDD 46 AVDD 4 AVDD 45 AVDD 5 CLK- 44 SYNC 6 CLK+ 43 VCM 7 AVDD 42 VREF 8 DRVDD 41 SENSE 9 D1-D 40 RBIAS 10 D1+D 39 AVDD 11 D0-D 38 VIN-B 12 D0+D 37 VIN+B 13 D1-C 36 VIN+A 14 D1+C 35 VIN-A 15 D0-C 34 AVDD 16 D0+C 33 PDWN 17 DCO- 32 CSB 18 DCO+ 31 SDIO/OLM 19 FCO- 30 SCLK/DTP 20 FCO+ 29 DRVDD 21 D1-B 28 D0+A 22 D1+B 27 D0-A 23 D0-B 26 D1+A 24 D0+B 25 D1-A NOTE: 1. The exposed thermal PAD on the bottom of the package provides the analog ground f
