1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Correct lead finish for device 03 on last page. Update boilerplate. - CFS 05-12-02 Thomas M. Hess B Correct operating case temperature for all device types in section 1.3 and 1.4. Add device type 04 to the table in section 6.3. - PHN 06-04-04 Thomas M. Hess
2、 C Update boilerplate paragraphs to current requirements. - PHN 11-11-29 Thomas M. Hess D Add device type 05 and 06 and case outline Y. - PHN 13-05-14 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance w
3、ith ASME Y14.24 Vendor item drawing REV D D D D D D D D D D D D D D D D D D D D D D PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 REV D D D D D D D D D D D D D D D D D D D D D D PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV D
4、D D D D D D D D D D D D D D D D PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC
5、SILICON YY MM DD 050607 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05607 REV D PAGE 1 OF 61 AMSC N/A 5962-V063-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDEN
6、T NO. 16236 DWG NO. V62/05607 REV D PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +105C (devices 01-03 and 05), -40C to +85C (device 04 and 06). 1.2 Ve
7、ndor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05607 - 01 X E Drawing Device type Case outline Lead finish number
8、 (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Clock Rate Circuit function 01 SM32C6416T-EP 600 MHz Fixed Point Digital Signal Processor 2/ 02 SM32C6416T-EP 720 MHz Fixed Point Digital Signal Processor 2/ 03 SM32C6416T-EP 850 MHz Fixed Point Digital Signal Processo
9、r 2/ 04 SM32C6416T-EP 1 GHz Fixed Point Digital Signal Processor 2/ 05 SM32C6416TB-EP 850 MHz Fixed Point Digital Signal Processor 2/ 06 SM32C6416TB-EP 1 GHz Fixed Point Digital Signal Processor 2/ 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Packag
10、e style X 532 Plastic ball grid array Y 532 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladiu
11、m Z Other 1/ Users are cautioned to review the manufacturers data manual for additional user information relating to these devices. 2/ Device type 01-04 are no longer available. Device type 05 should have similar specifications and same temperature range as the 03 device. Device type 06 should have
12、similar specifications and same temperature range as the 04 device. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 3 1.3 Absolute maximum ratings
13、. 3/ Supply voltage ranges: (CVDD) . -0.5 V to +1.5 V 4/ (DVDD) -0.5 V to +4.4 V 4/ Input voltage ranges: (VI), (except PCI) . -0.5 V to +4.4 V (VIP), (PCI) . -0.5 V to DVDD+ 0.5 V Output voltage ranges: (VO) (except PCI) -0.5 V to +4.4 V (VOP), (PCI) -0.5 V to DVDD+ 0.5 V Operating case temperature
14、 ranges, (TC): Device type 01-03,05 . -40C to +105C Device type 04, 06 -40C to +85C Storage temperature range, (TSTG) . -65C to +150C 1.4 Recommended operating conditions. Supply voltage, core (CVDD) (device type 01) . +1.05 V to +1.16 V 5/ Supply voltage, core (CVDD) (device type 02-04) +1.16 V to
15、+1.24 V 5/ 6/ Supply voltage, I/O (DVDD) . +3.14 V to +3.46 V Supply ground, (VSS) 0 V Minimum high level input voltage, (VIH) (except PCI) . +2.0 V Maximum low level input voltage, (VIL) (except PCI) +0.8 V Input voltage, (VIP) (PCI) . -0.5 V to DVDD+ 0.5 V High level input voltage (VIHP) (PCI) 0.5
16、DVDDto DVDD+ 0.5 V Low level input voltage, (VILP) (PCI) . -0.5 V to 0.3DVDDOperating case temperature (TC): Device type 01-03, 05: -40C to +105C Device type 04, 06: . -40C to +85C 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are str
17、ess ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 4/ All voltage values are with r
18、espect to VSS. 5/ Future variants of these devices may operate at voltage ranging from 1.0 V to 1.2 V to provide a range of system power/performance options. Manufacturer highly recommends that users design in a supply that can handle multiple voltages within this range ( with 3% tolerances) by impl
19、ementing simple board changes such as reference resistor values or input pin configuration modifications. Not incorporating a flexible supply may limit the systems ability to easily adapt future versions of these devices. 6/ Device type 01 and 02 are product preview devices. Provided by IHSNot for R
20、esaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 4 1.4 Recommended operating conditions - Continued. Thermal resistance characteristics case X: Air Flow (m/s) 7/ C/W 8/ C/
21、W (with heat sink 9/) 1 Junction to case, RJCN/A 3.11 3.11 2 Junction to board, RJBN/A 9.95 9.95 3 Junction to free air, RJA0.00 19.6 14.4 4 Junction to free air, RJA0.5 17.3 11.5 5 Junction to free air, RJA1.0 15.6 9.3 6 Junction to free air, RJA2.0 14.7 8.0 7 Junction to package top, PsiJTN/A 0.83
22、 0.83 8 Junction to board PsiJBN/A 7.88 7.88 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Associati
23、on, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification
24、 (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4
25、, and table I herein. 7/ m/s = meter per second 8/ Numbers are based on simulation 9/ When operating at 1 GHz, a heat sink is required to reduce the thermal resistance characteristics of the package. See manufacturer data for more information. Provided by IHSNot for ResaleNo reproduction or networki
26、ng permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 5 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case ou
27、tline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Timing reference. The timing reference circuit for AC timing meas
28、urements shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figures 5-40. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG
29、 NO. V62/05607 REV D PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition At recommended operating ranges unless otherwise noted Device type Limits Unit Min Max High level output voltage (except PCI) VOHDVDD= Min, IOH= Max All 2.4 V High level output voltage (PCI) VO
30、HPIOHP= -0.5 mA, DVDD= 3.3 V 0.9DVDD 2/ Low level output voltage (except PCI) VOLDVDD= Min, IOL= Max 0.4 Low level output voltage (PCI) VOLPIOLP= 1.5 mA, DVDD= 3.3 V 0.1DVDD 2/ Input current (except PCI)dc IIVI= VSSto DVDDno opposing internal resistor 1 A VI= VSSto DVDDopposing internal pullup resis
31、tor 3/ -200 -50 VI= VSSto DVDDno opposing internal pulldown resistor 3/ 50 200 Input leakage current (PCI)dc 4/ IIP0 VIP DVDD= 3.3 V, 10 High level output current dc IOHEMIF, CLKOUT4, CLKOUT6, EMUx -8 mA Timer, UTOPIA, TDO, GPIO (Excluding GP15:9, 2, 1), McBSP -4 PCI/HPI -0.5 2/ Low level output cur
32、rent dc IOLEMIF, CLKOUT4, CLKOUT6, EMUx 8 Timer, UTOPIA, TDO, GPIO (Excluding GP15:9, 2, 1), McBSP 4 PCI/HPI 1.5 2/ Off state output current dc IOZVO= DVDDor 0 V 20 A Core supply current 5/ ICDDCVDD= 1.2 V, CPU clock = 720 MHz 6/ 713 Typ mA CVDD= 1.2 V, CPU clock = 850 MHz 824 Typ CVDD= 1.2 V, CPU c
33、lock = 1GHz 6/ 952 Typ CVDD= 1.1 V, CPU clock = 600 MHz 6/ 558 Typ I/O supply current 5/ IDDDDVDD= 3.3 V, CPU clock = 600 MHz 6/ 151 Typ Input capacitance CI2 pF Output capacitance CO3 See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
34、m IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 7 TABLE I. Electrical performance characteristics - Continued. 1/ No. Test Symbol Test condition At recommended operating ranges unless otherwise noted Limits Unit PLL Mode x20 PLL Mode
35、x12 PLL Mode x6 x1 (Bypass) Min Max Min Max Min Max Min Max INPUT AND OUTPUT CLOCKS Timing requirements for CLKIN for device type 01 7/ 8/ 9/ 1 Cycle time, CLKIN tc(CLKIN)See figure 6 33.3 40 20 23.8 13.3 23.8 0 10 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.4C 0.4C 0.45C 3 Pulse duration, CLKI
36、N low tw(CLKINL)0.4C 0.4C 0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 5 1 5 Period jitter, CLKIN tJ(CLKIN)0.02C 0.02C 0.02C 0.02C Timing requirements for CLKIN for device type 02 7/ 8/ 9/ 1 Cycle time, CLKIN tc(CLKIN)See figure 6 27.7 40 16 23.8 13.3 23.8 0 10 ns 2 Pulse duration, CLKIN high tw
37、(CLKINH)0.4C 0.4C 0.4C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.4C 0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 5 1 5 Period jitter, CLKIN tJ(CLKIN)0.02C 0.02C 0.02C 0.02C Timing requirements for CLKIN for device type 03, 05 7/ 8/ 9/ 1 Cycle time, CLKIN tc(CLKIN)See figure 6 23.5 40 14
38、 23.8 13.3 23.8 0 10 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.4C 0.4C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.4C 0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 5 1 5 Period jitter, CLKIN tJ(CLKIN)0.02C 0.02C 0.02C 0.02C Timing requirements for CLKIN for device type 04, 06 7/ 8/
39、9/ 1 Cycle time, CLKIN tc(CLKIN)See figure 6 23.5 40 14 23.8 13.3 23.8 0 10 ns 2 Pulse duration, CLKIN high tw(CLKINH)0.4C 0.4C 0.4C 0.45C 3 Pulse duration, CLKIN low tw(CLKINL)0.4C 0.4C 0.4C 0.45C 4 Transition time, CLKIN tt(CLKIN)5 5 5 1 5 Period jitter, CLKIN tJ(CLKIN)0.02C 0.02C 0.02C 0.02C See
40、notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1 No. Test S
41、ymbol Test condition At recommended operating ranges unless otherwise noted Device types: All Limits Unit CLKMODE = X1, X6, X12, X20 Min Max INPUT AND OUTPUT CLOCKS (CONTINUED) Switching characteristics for CLKOUT4 10/ 11/ 12/ 1 Period jitter, CLKOUT4 tj(CKO4)See figure 7 0 175 ps 2 Pulse duration,
42、CLKOUT4 high tw(CKO4H)2P-0.7 2P+0.7 ns 3 Pulse duration, CLKOUT4 low tw(CKO4L)2P-0.7 2P+0.7 4 Transaction time, CLKOUT4 tt(CKO4)1 Switching characteristics for CLKOUT6 10/ 11/ 12/ 1 Period jitter, CLKOUT6 tj(CKO6)See figure 7 0 175 ps 2 Pulse duration, CLKOUT6 high tw(CKO6H)3P-0.7 3P+0.7 ns 3 Pulse
43、duration, CLKOUT6 low tw(CKO6L)3P-0.7 3P+0.7 4 Transaction time, CLKOUT6 tt(CKO6)1 Timing requirements for ECLKIN for EMIFA and EMIFB 7/ 12/ 13/ 1 Cycle time, ECLKIN tc(EKI)See figure 8 CVDD= 1.2 V 6 15/ 16P ns CVDD= 1.1 V 7.5 15/ 16P 2 Pulse duration, ECLKIN high tw(EHIH)2.7 3 Pulse duration, ECLKI
44、N low tw(EKIL)2.7 4 Transaction, ECLKIN tt(EKI)2 Switching characteristics for ECLKOUT1 for EMIFA and EMIFB modules 10/ 13/ 14/ 16/ 1 Period jitter, ECLKOUT1 tj(EKO1)See figure 8 0 175 17/ ps 2 Pulse duration, ECLKOUT1 high tw(EKO1H)EH-0.7 EH+0.7 ns 3 Pulse duration, ECLKOUT1 low tw(EKO1L)EL-0.7 EL+
45、0.7 4 Transition time, ECLKOUT1 tt(EKO1)1 5 Delay time, ECLKIN high to ECLKOUT1 high td(EKIH-EKO1L)0.8 8 6 Delay time, ECLKIN low to ECLKOUT1 low td(EKIL-EKO1L)0.8 8 Switching characteristics for ECLKOUT2 for EMIFA and EMIFB modules 10/ 13/ 18/ 1 Period jitter, ECLKOUT2 tj(EKO2)See figure 8 0 175 17
46、/ ps 2 Pulse duration, ECLKOUT2 high tw(EKO2H)0.5NE-0.7 0.5NE+0.7 ns 3 Pulse duration, ECLKOUT2 low tw(EKO2L)0.5NE-0.7 0.5NE+0.7 4 Transition time, ECLKOUT2 tt(EKO2)1 5 Delay time, ECLKIN high to ECLKOUT2 high td(EKIH-EKO2L)3 8 6 Delay time, ECLKIN low to ECLKOUT2 low td(EKIL-EKO2L)3 8 See notes at
47、end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05607 REV D PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1 No Test Symbol Test
48、 condition At recommended operating ranges unless otherwise noted Device types: All Limits Unit Min Max ASYNCHRONOUS MEMORY TIMING Timing requirements for asynchronous memory cycles for EMIFA module 13/ 19/ 20/ 3 Setup time, EDx valid before ARE high tsu(EDV-AREH)See figure 9 and 10 6.5 ns 4 Hold time, EDx valid after ARE high th(AREH-EDV)1 6 Setup time, ARDY valid before ECLKOUTx hig
