1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. ksr 09-12-03 Charles Saffle REV SHET REV A A A A A A A A A A A A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV A A A A A A A
2、A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY R
3、aymond Monnin MICROCIRCUIT MEMORY CMOS, DIGITAL, 256M X 8 Bit STACKED DIE (2Gbit) SYNCHRONOUS DRAM (SDRAM), MODULE AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 03 02 07 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-02518 SHEET 1 OF 34 DSCC FORM 2233 APR 97 5962-E322-09 Pro
4、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three prod
5、uct assurance class levels consisting of space application (device Class V), high reliability (device classes M and Q), and nontraditional performance environment (device Class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Wh
6、en available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device Class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 02518 01 N X B Federal stock
7、 class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device Classes N, Q, and V RHA marked devices meet the MIL-PRF- 38535 specified RHA levels and are marked wi
8、th appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify 128M x 8 bit SDRAM circuits utilizing vertical stacking technology as follows: Device Type Generic Number Circuit Function No. Die in Stack 01 SD256Mx88 16M x 8 bit x 16 bank, sync
9、hronous DRAM (2 Gbit) 8 Dice 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device Class Device Requirements Documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN Class Level
10、 B microcircuits in accordance with MIL-PRF-38535, Appendix A 1/ N Certification and qualification to MIL-PRF-38535 with a nontraditional performance environment (encapsulated in plastic). Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as desig
11、nated in MIL-STD-1835 and as follows: Outline Letter Descriptive Designator Terminals Package Style X See figure 1 54 Plastic small outline package 1.2.5 Lead Finish. The lead finish is as specified in MIL-PRF-38535 for device Classes N, Q, V. 1/ For this drawing, device class M shall not apply. Pro
12、vided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage ra
13、nge, (VCC) - -0.5 V dc to +4.6 V dc Voltage range on any input pin - -0.5 V dc to +4.6 V dc Voltage range on any output pin - -0.5 V dc to Vcc +0.5 V dc Short-circuit output current - 50 mA Power dissipation - 2 W Operating free-air temperature range, (TA) - -40C to +85C Storage temperature range, (
14、TSIG) - -55C to +125C Thermal resistance, junction-to-case, (JC): Case X - 15C/W 1.4 Recommended operating conditions. Supply voltage range, (VCC) - +3.0 V dc to +3.6 V dc Supply voltage, (VSS) - 0 V dc High-level input voltage, (VIH) - +2.0 V dc to Vcc +0.3 V dc Low-level input voltage, (VIL) - -0.
15、3 V dc to +0.8 V dc Operating free-air temperature range, (TA) - -40C to +85C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified,
16、the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface
17、 Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization D
18、ocument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable
19、 laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management
20、(QM) plan. The modification in the QM plan shall not affect the form, fit or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions for device classes N, Q and V shall be as specified in MIL-PRF-38535 and herein. 3.2.1 Case
21、outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum lev
22、els may degrade performance and affect reliability. 3/ All voltage values in this drawing are with respect to VSS Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS,
23、 OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Block or logic diagram(s). The block or logic diagram(s) shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as speci
24、fied on figure 5. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperat
25、ure range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in Table IIA. The electrical tests for each subgroup are defined in Table I. 3.4.1 Functional Tests. Listed below is a set of required test patterns to be used in conjunction with table I f
26、or the functional tests of Subgroups 7, 8A, and 8B as well as the A.C. parametric tests in Subgroups 9, 10 and 11. These tests have been determined to effectively stress sensitivities related to address and data pattern as well as functionally test the device to be supplied to this specification. A.
27、C. parametric limits are tested by using the limit values as input conditions and measurement delays of the timing sets associated with Subgroups 7, 8A, and 8B. Additional test patterns may also be used. a. Walking 0101 Pattern Full Page Burst / Sequential (Vmin) b. Walking FEFE Pattern Full Page Bu
28、rst / Sequential (Vmax) c. March 00/FF Pattern 8 Byte Burst / Interleave (Vmin) d. March FF/00 Pattern 8 Byte Burst / Interleave (Vmax) e. March AA/55 Pattern 8 Byte Burst / Interleave (Vmin) f. March 55/AA Pattern 8 Byte Burst / Interleave (Vmax) g. March FF/00 Pattern 1 Byte Burst / Sequential (Vm
29、in) h. March 00/FF Pattern 1 Byte Burst / Sequential (Vmax) i. March 66/33 Pattern 1 Byte Burst / Sequential (Vmin) j. March 33/66 Pattern 1 Byte Burst / Sequential (Vmax) k. Refresh Pause Checkerboard (Vmin) l. Refresh Pause Checkerboard (Vmax) m. Refresh Pause Checkerboard Bar (Vmin) n. Refresh Pa
30、use Checkerboard Bar (Vmax) 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking
31、 the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q and V shall be a “QML“ or “Q“
32、 as required in MIL-PRF-38535. 3.6 Certificate of compliance. A certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approv
33、ed source of supply for this drawing shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 shall be provided with each lot of microcircui
34、ts delivered to this drawing. 4. VERIFICATION. 4.1 Sampling and inspection. For device classes N, Q, and V, sampling and inspection procedure shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not a
35、ffect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR
36、 97 4.2 Screening. For device classes N, Q, and V screening shall be in accordance with MIL-PRF-38535, the manufacturers QM plan, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes N, Q, and V. a. Temperatu
37、re and voltage accelerated burn-in shall be employed for the SDRAM. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
38、document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable
39、, in accordance with the intent specified in method 1015 of MIL-STD-883. (1) TA= +135C, VCC= 4.0 V (2) Test duration: 72 hours for classes N but at burst write, burst stop and RAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”. 3. Burst stop
40、 is valid at every burst length. FIGURE 5. Timing waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 29
41、DSCC FORM 2234 APR 97 Notes: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge
42、command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. FIGURE 5. Timing waveforms Continued.
43、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-02518 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 30 DSCC FORM 2234 APR 97 Notes: 1. BRSW modes is enabled by setting A9 “Hi
44、gh” at MRS(Mode Register Set). At the BRSW Mode the burst length at write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep in mind that tRASshould not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. FIGURE 5. Timing waveforms Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
