1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-08-27 Charles F. Saffle REV SHEET REV A A A A SHEET 15 16 17 18 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY R
2、ajesh Pithadia DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Robert M. Heber MICROCIRCUIT, DIGITAL-L
3、INEAR, 14-BIT, 400 MSPS DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 07-08-22 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-07204 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E549-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
4、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application
5、 (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 07204 0
6、1 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA level
7、s and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 DAC5675A 14 bit, 400 MSPS digital-to-analog converter 1.2.3 Device class designat
8、or. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline are as designated in MIL-STD-1835 and as follows: Outline
9、 letter Descriptive designator Terminals Package style X See figure 1 52 Quad flat pack with non-conductive tie bar 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro
10、m IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range: AVDD-0.3 V to +3.6 V 2/ DVDD-0.3 V to +3.6 V 3/ AVDDto DVDD. -3.6 V to +3.6 V Voltage betwee
11、n AGND and DGND -0.3 V to +0.5 V CLK, CLKC -0.3 V to AVDD+0.3 V 2/ Digital input D130A, D130B 3/, SLEEP, DLLOFF . -0.3 V to DVDD+0.3 V IOUT1, OUT2 -1 V to AVDD+ 0.3 V 2/ EXTIO, BIAS -1 V to AVDD+ 0.3 V 2/ Peak input current (any input) 20 mA Peak total input current (all inputs) -30 mA Storage tempe
12、rature range (TSTG) -65C to +150C Lead temperature 1.6 mm (1/16 inch) from the case for 10 seconds +260C Thermal resistance, junction-to-ambient (JA) 21.813C/W 4/, 5/ Thermal resistance, junction-to-case (JC) . 0.849C/W 4/, 5/, 6/ 1.4 Recommended operating conditions. Supply voltage : AVDD3.3 V DVDD
13、3.3 V Operating free-air temperature range (TA) -55C to +125C Estimated device life at elevated temperatures electromigration fail modes: _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and aff
14、ect reliability. 2/ Measured with respect to AGND. 3/ Measured with respect to DGND. 4/ Heat slug connected to PCB thermal plane. Airflow is at 0 LFM (no airflow). 5/ Specified with the thermal bond pad on the backside of the package soldered to a 2 ounce CU plate PCB thermal plane. 6/ Per MIL-STD-8
15、83 method 1012.1. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government sp
16、ecification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-
17、PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcirc
18、uit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflic
19、t between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requi
20、rements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and ph
21、ysical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be
22、 as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveform. The timing waveform shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the e
23、lectrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical te
24、sts for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the opt
25、ion of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “
26、QML“ or “Q“ as required in MIL-PRF-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electric
27、al performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Resolution 1, 2, 3 All 14 Bit DC accuracy section 2/ Integral nonlinearity INL 1, 2, 3 All -4 4.6 LSB Differential nonlinearity DNL 1, 2 -2 2.2 LSB 3 -
28、2 2.5 Analog output section Full scale output current IO(FS)1, 2, 3 All 2 20 mA Output compliance range AVDD= 3.15 V to 3.45 V, IO(FS)= 20 mA 1, 2, 3 AVDD- 1 AVDD+ 0.3 V Gain error Without internal reference 1, 2, 3 -10 10 %FSR With internal reference -10 10 Output resistance 1 300 typical k Output
29、capacitance 1 5 typical pF Reference output section Reference voltage V(EXTIO)1, 2, 3 All 1.17 1.3 V Reference input section Input reference voltage V(EXTIO)1, 2, 3 All 0.6 1.25 V Input resistance RIN1 1 typical M Input capacitance CIN1 100 typical pF Power supply section Analog supply voltage AVDD1
30、, 2, 3 All 3.15 3.6 V Digital supply voltage DVDD1, 2, 3 3.15 3.6 V Power dissipation PDAVDD= 3.3 V, DVDD= 3.3 V 1, 2, 3 900 mW Analog and digital power supply rejection ratio APSRR AVDD= 3.15 to 3.45 V 1, 2, 3 -0.9 0.9 %FSR/V DPSRR -0.9 0.9 Analog supply current I(AVDD)3/ 1, 2, 3 148 mA Digital sup
31、ply current I(DVDD)3/ 1, 2, 3 130 mA Analog output section Output update rate fCLK9, 10, 11 All 400 MSPS See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARIT
32、IME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max AC linearity section Total harmonic distortion
33、THD fCLK= 400 MSPS, fOUT= 20.0 MHz 9, 10 All 60 dBc fCLK= 400 MSPS, fOUT= 20.0 MHz, for TMIN11 57 Spurious free dynamic range to Nyquist 4/, 5/ SFDR fCLK= 400 MSPS, fOUT= 20.0 MHz 9, 10 62 dBc fCLK= 400 MSPS, fOUT= 20.0 MHz, for TMIN11 61 Signal-to-Noise Ratio SNR fCLK= 400 MSPS, fOUT= 20.0 MHz 9, 1
34、0, 11 60 dBc LVDS interface section: nodes D130A, D130B Internal termination impedance ZT1, 2, 3 All 90 132 Input capacitance CI1 2 typical pF CMOS interface (SLEEP) section High level input voltage VIH1, 2, 3 All 2 V Low level input voltage VIL1, 2, 3 0.8 V High level input current IIH1, 2, 3 -100
35、100 A Low level input current IIL1, 2, 3 -10 10 A Input capacitance CI1 2 typical pF Clock interface (CLK, CLKC) section Clock differential input voltage |CLK-CLKC| 9, 10, 11 All 0.4 0.8 VPPClock duty cycle 9, 10, 11 40 60 % Common mode voltage range VCM9, 10, 11 1.6 2.4 V Input resistance Node CLK,
36、 CLKC 1 670 typical Input capacitance Node CLK, CLKC 1 2 typical pF Input resistance Differential 1 1.3 typical k Input capacitance Differential 1 1 typical pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI
37、CROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit
38、Min Max Timing section Input setup time tSU9, 10, 11 All 1.5 ns Input hold time tH9, 10, 11 0 ns 1/ Unless otherwise specified, AVDD= 3.3 V, DVDD= 3.3 V, IO(FS)= 20 mA, differential transformer-coupled output, and 50 doubly terminated load. 2/ Measured differential at IOUT1and IOUT2; 25 to AVDD. 3/
39、Measured at fCLK= 400 MSPS and fOUT= 70 MHz. 4/ See figure 5. 5/ See figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DS
40、CC FORM 2234 APR 97 Case X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 Case X D
41、imensions Symbol Inches Millimeters Min Max Min Max A1 - 0.090 - 2.29 A2 - 0.105 - 2.68 A3 0.002 0.014 0.05 0.36 A4 0.03 BSC 0.762 BSC b 0.006 0.010 0.15 0.25 c 0.004 0.008 0.10 0.20 D1/E1 0.542 0.558 13.77 14.17 D2/E2 0.300 BSC 7.62 BSC D3/E3 0.940 0.960 23.88 24.38 D4/E4 0.394 BSC 10.0 BSC e 0.025
42、 BSC 0.64 BSC F 0.125 0.145 3.18 3.68 J 0.030 0.040 0.76 1.02 K - 0.020 - 0.51 K1 - 0.018 - 0.46 L 1.584 1.616 40.23 41.05 N 52 NOTES: 1. Controlling dimensions are inches, millimeter dimensions are given for reference only. 2. Ceramic quad flat pack with flat leads brazed to non-conductive tie bar
43、carrier. 3. This package is hermetically sealed with a metal lid. 4. The leads are gold plated and can be solder dipped. 5. All leads are not shown for clarity purposes. 6. Lid and heat sink are connected to GND leads. FIGURE 1. Case outline continued. Provided by IHSNot for ResaleNo reproduction or
44、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 Device type All Device type All Case outline X Case outline X Terminal number Terminal symbol Terminal nu
45、mber Terminal symbol 1 D13A 27 D5A 2 D13B 28 D5B 3 D12A 29 D4A 4 D12B 30 D4B 5 D11A 31 D3A 6 D11B 32 D3B 7 D10A 33 D2A 8 D10B 34 D2B 9 D9A 35 D1A 10 D9B 36 D1B 11 D8A 37 D0A 12 D8B 38 D0B 13 AGND 39 AGND 14 D7A 40 SLEEP 15 D7B 41 NC 16 DVDD42 BIASJ 17 DGND 43 EXTIO 18 DVDD44 AGND 19 DGND 45 AVDD20 A
46、GND 46 IOUT1 21 AVDD47 IOUT2 22 CLKC 48 AVDD23 CLK 49 AGND 24 D6A 50 AGND 25 D6B 51 AVDD26 AGND 52 AGND FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07204 DLA LAND AND MARIT
47、IME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 11 DSCC FORM 2234 APR 97 Terminal I/O Description AGND I Analog negative supply voltage (ground); pin 13 internally connected to the heat slug and lid (lid is also grounded internally). AVDDI Analog positive supply voltage BIASJ O Full scale outpu
48、t current bias. CLK I External clock input CLKC I Complementary external clock D13A D0A I LVDS positive input, data bits 13 through 0. D13A is the most significant data bit (MSB). D0A is the least significant data bit (LSB). D13B D0B I LVDS negative input, data bits 13 through 0. D13B is the most significant data bit (MSB). D0B is the leas
