1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Phu H. N
2、guyen COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, 3.3-V HIGH PERFORMANCE CLOCK AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 09-10-01 SYNCHRONIZER AND JITTE
3、R CLEANER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-07230 SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E279-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CE
4、NTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finish
5、es are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 07230 01 V X C Federal stock class designator RHA designator (see 1
6、.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device
7、 class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit functio
8、n 01 CDCM7005M 3.3-V High performance clock synchronizer and jitter cleaner 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements
9、 for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Term
10、inals Package style X See figure 1. 52 Quad flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN
11、DARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC, AVCC, VCC_CP) -0.5 V to 4.6 V 2/ Input voltage range (VI) -0.5 V to VCC+ 0.5 V 3/ Output volta
12、ge range (VO) -0.5 V to VCC+ 0.5 V 3/ Input current (IIN) (VINVCC) 20 mA Output current for LVPECL/LVCMOS outputs (IO) (0 V VO VCC) . 50 mA Storage temperature range (Tstg) . -65C to +150C Maximum junction temperature (TJ) . +125C Thermal resistance, junction-to-ambient (RJA) 21.813C/W 4/ 5/ Thermal
13、 resistance, junction-to-case (RJC) . 0.849C/W 4/ 6/ 1.4 Recommended operating conditions. Supply voltage range: VCC, AVCC. 3 V to 3.6 V VCC_CP. 2.3 V to VCCMaximum low-level input voltage, LVCMOS (VIL) . 0.3 x VCC7/ Minimum high-level input voltage, LVCMOS (VIH) 0.7 x VCC7/ Maximum high-level outpu
14、t current, LVCMOS (IOH) . -8 mA 8/ Maximum low-level output current, LVCMOS (IOL) . 8 mA 8/ Input voltage range, LVCMOS (VI) . 0 V to 3.6 V Input amplitude range, LVPECL (VINPP) . 0.5 V to 1.3 V 9/ Common-mode input voltage range, LVPECL (VIC) . 1 V to VCC 0.3 V Operating case temperature range (TC)
15、 . -55C to +125C _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. These are stress ratings only and functional operation of the device at these or any other conditions be
16、yond those under recommended operating conditions are not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. See operating life derating chart above. 2/ All supply voltages have to be supplied at the same time. 3/ The input and output negative
17、voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 4/ Connected to GND with nine thermal vias (0.3 mm diameter). 5/ Board mounted, per JESD51-5. 6 Per MIL-STD-883 method 1012. 7/ VILand VIHare required to maintain ac specifications; the actual device function
18、 tolerates a smaller input level of 1 V, if an ac-coupling to VCC/2 is provided. 8/ Includes all status pins. 9/ VINPPminimum and maximum are required to maintain ac specifications; the actual device function tolerates a minimum VINPPof 150 mV. Provided by IHSNot for ResaleNo reproduction or network
19、ing permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification
20、, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specificat
21、ion for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copi
22、es of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of th
23、is document to the extent specified herein. Unless otherwise specified, the issues of documents are the issues of the documents cited in the solicitation. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JESD51-5 - Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms
24、(Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of thi
25、s drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as
26、 specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for no
27、n-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Cas
28、e outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms and load c
29、ircuit. The timing waveforms and load circuit shall be as specified on figures 4 - 14. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION L
30、EVEL SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operat
31、ing temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufactur
32、ers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device clas
33、ses Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark fo
34、r device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For devic
35、e class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm tha
36、t the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-
37、38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this dra
38、wing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be m
39、ade available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted w
40、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group
41、A subgroups Device type Limits Unit Min Max Overall Device Characteristics Supply current (ICCover frequency) 2/ ICC_LVPECLfVCXO= 200 MHz, fREF_IN= 25 MHz, PFD = 195.3125 kHZ, ICP= 2 mA, All outputs are LVPECL and Div-by-8. For load, see figure 5. 1, 2, 3 All 260 mA ICC_LVCMOSfVCXO= 200 MHz, fREF_IN
42、= 25 MHz, PFD = 195.3125 kHZ, ICP= 2 mA, All outputs are LVCMOS and Div-by-8. Load = 10 pF. 1, 2, 3 All 160 mA Power-down current ICCPDfIN= 0 MHz, VCC= 3.6 V, AVCC= 3.6 V, VCC_CP= 3.6V, VI= 0 V or VCC1, 2, 3 All 300 A High-impedance state output current for Yx outputs IOZVO= 0 V or VCC 0.8 V 1, 2, 3
43、 All 40 A VO= 0 V or VCC100 Voltage on I_REF_CP (external current path for accurate charge pump current) VI_REF_CP12 k to GND at pin 49. 1, 2, 3 All 1.114 1.326 V Output reference voltage VBBVCC= 3 V to 3.6 V; IBB= -0.2 mA 1, 2, 3 All VCC 1.446 VCC 1.090 V Output capacitance for Yx COVCC= 3.3 V, VO=
44、 0 V or VCC4 All 3 TYP 3/ pF Input capacitance at PRI_REF and SEC_REF CIVI= 0 V or VCC4 All 3.6 TYP 3/ pF Input capacitance at CTRL_LE, CTRL_CLOCK, and CTRL_DATA VI= 0 V or VCC3 TYP 3/ See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license
45、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-07230 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified Group A
46、subgroups Device type Limits Unit Min Max LVCMOS Device Characteristics Output frequency 4/ 5/ 6/ fclkLoad = 5 pF to GND, 1 k to VCC, 1 k to GND 9, 10, 11 All 240 TYP 3/ MHz LVCMOS input clamp voltage VIKVCC= 3 V, II= -18 mA 1, 2, 3 All -1.2 V LVCMOS input current for CTRL_LE, CTRL_CLOCK and CTRL_DA
47、TA IIVI= 0 V or VCC, VCC= 3.6 V 1, 2, 3 All 5 A LVCMOS input current for PD, RESET, HOLD REF_SEL, PRI_REF, and SEC_REF 7/ IIHVI= VCC, VCC= 3.6 V 1, 2, 3 All 5 A LVCMOS input current for PD, RESET, HOLD REF_SEL, PRI_REF, and SEC_REF 7/ IILVI= 0 V, VCC= 3.6 V 1, 2, 3 All -15 -35 A High-level output vo
48、ltage for LVCMOS outputs VOHVCC= 3 V to 3.6 V, IOH= -100 A 1, 2, 3 All VCC 0.1 V VCC= 3 V, IOH= -6 mA 2.4 VCC= 3 V, IOH= -12 mA 2 Low-level output voltage for LVCMOS outputs VOLVCC= 3 V to 3.6 V, IOL= 100 A 1, 2, 3 All 0.1 V VCC= 3 V, IOL= 6 mA 0.5 VCC= 3 V, IOL= 12 mA 0.8 High-level output current IOHVCC= 3.3 V, VO= 1.65 V 1, 2, 3 All -50 -20 mA Low-level output current IOLVCC= 3.3 V, VO= 1.65 V 1, 2, 3 All 20 50 mA Phase offset (REF_IN to Y output) 8/ tphoVREF_IN = VCC/2, Y = VCC/2 See figure 8, Load = 10 pF 9, 10, 11 All 2.7 TYP 3/ ns LVCMOS pulse skew 9/ t
