1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.
2、mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Laura Leeper THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4MEG X 32-BIT (128M), RADIATION-HARDENED, DUAL VOLTAGE SRAM with embedded EDAC,
3、MULTICHIP MODULE DRAWING APPROVAL DATE 13-01-11 AMSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-10204 SHEET 1 OF 31 DSCC FORM 2233 APR 97 5962-E143-13 1. SCOPE Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5
4、962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finis
5、hes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 10204 01 Q X A Federal RHA Device Device Case Lead stock cl
6、ass designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desi
7、gnator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 UT8ER4M32M 4M X 32-bit rad-hard SRAM master 25 ns 02 UT8ER4M32S 4M X 32-bit rad-hard SRAM slave 25 ns 03 UT8E
8、R4M32M 4M X 32-bit rad-hard SRAM master, with additional screening 1/ 25 ns 04 UT8ER4M32S 4M X 32-bit rad-hard SRAM slave, with additional screening 1/ 25 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device
9、 class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 132 dual cavity quad flat pack
10、 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. 1/ Device types 03 and 04 provides QML Q product with additional testing as specified in paragraph 4.2.1d. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,
11、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (VDD1) . -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) . -0.3 V dc to +3.8 V dc Voltage range
12、on any pin . -0.3 V dc to +3.8 V dc Input current, dc . + 10 mA Power dissipation permitted, PD TC= 105C 1.3 W 4/ Case temperature range, (TC) . -55C to +105C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, junction-to-case, (JC): Case X 15C/W 1
13、.4 Recommended operating conditions. 3/ Supply voltage range, (VDD1) . +1.7 V dc to +2.0 V dc Supply voltage range, (VDD2) . +2.3 V dc to +3.6 V dc Supply voltage, (VSS) . 0 V dc Input voltage, dc 0 V dc to VDD2Case operating temperature range, (TC) -55C to +105C 1.5 Radiation features Maximum total
14、 dose available (effective dose rate = 1 rads(Si)/s). 10.0 x 104rads(Si) 5/ Single event phenomenon (SEP) effective linear energy threshold (LET) with no upsets N/A 6/ with no latch-up . 100 errors or 106ions/cm2. c. The flux shall be between 102and 105ions/cm2/s. The cross-section shall be verified
15、 to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The test temperature shall be +25C 10C for single event upset testing and at the maximum rated operating temperature +10C
16、for single event upset testing. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204
17、 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 13 DSCC FORM 2234 APR 97 Case outline X FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIM
18、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 14 DSCC FORM 2234 APR 97 Case outline X Symbol Millimeters Inches Min Max Min Max A 7.87 .310 A1 6.02 .237 A2 3.61 .142 A3 2.14 2.54 .084 .100 A4 0.59 0.69 .023 .027 b 0.150 0.250 .006 .010 c 0.125 0.200 .005 .008 e 0.635 0.025 D/E 37.34 38.36 1.47 1.
19、51 D1/E1 22.63 23.09 .891 .909 D2/E2 21.64 22.04 .852 .868 D3/E3 20.12 20.52 .792 .808 Q 0.305 0.012 Q1 1.0 0.039 Q2 0.25 0.009 Q3 1.0 0.039 R 0.25 0.009 NOTES: 1. Item was originally designed in millimeters. 2. All exposed metal and metalized areas shall be gold plated per MIL-PRF-38535. 3. The sea
20、l ring and lids are electrically connected to VSS. 4. Dogleg geometries optional within dimensions shown. 5. Lead finish is in accordance with MIL-PRF-38535. 6. Tie bar may have excise slots of various configurations and are vendor option. Tie bar dimensions are for reference only. 7. Package materi
21、al: opaque 90% minimum Alumina ceramic. 8. ESD classification mark or dot is located in the pin 1 corner within area shown. 9. Q provides the clearance of the bottom lid and the circuit board. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted wi
22、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 15 DSCC FORM 2234 APR 97 Case X Device type All Device type All Case outline X Case outline X Terminal number Terminal symbol Terminal number Terminal symbo
23、l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VSS VSS DQ0 DQ1 DQ2 DQ3 VDD2 VSS DQ4 DQ5 DQ6 DQ7 VDD1 VSS NC VDD2 NC VDD2 NC VSS VDD1 DQ8 DQ9 DQ10 DQ11 VSS VDD2 DQ12 DQ13 DQ14 DQ15 VSS VSS VSS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
24、55 56 57 58 59 60 61 62 63 64 65 66 67 68 A11 A12 A13 VSS NC NC NC VSS BUSY. 1/ VDD1 E7 E5 E3 E1 VDD1 G VSS E2 E4 E6 E8 VDD1 SCRUB MBE VDD2 NC NC VSS A14 A15 A16 VSS VSS VSS FIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-
25、,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 16 DSCC FORM 2234 APR 97 Case X Continued. Device type All Device type All Case outline X Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 69 70 71 7
26、2 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 DQ31 DQ30 DQ29 DQ28 VDD2 VSS DQ27 DQ26 DQ25 DQ24 VDD1 VSS NC VDD2 NC VDD2 NC VSS VDD1 DQ23 DQ22 DQ21 DQ20 VSS VDD2 DQ19 DQ18 DQ17 DQ16 VSS VSS VSS VSS 102 103 104 105 106 107 108 109 110 111 112 113 114 115 11
27、6 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 A10 A9 A8 A7 VDD1 VSS A6 W A18 NC VDD1 NC NC VDD1 NC VSS NC NC VDD1 NC A17 A5 A4 VSS VDD1 A3 A2 A1 A0 VSS VSS 1/ Device types 01 and 03 = BUSY. Device types 02 and 04 = NC FIGURE 2. Terminal connections Continued. Provided by IHSNot f
28、or ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 17 DSCC FORM 2234 APR 97 SRAM Device Control Operation Truth Table 1/ Only one enable may be active at an
29、y given time. Note : L=low, H=high, X= dont care, Z=high impedance EDAC Control Pin Operation Truth Table MBE SCRUB BUSY I/O Mode Mode H H H Read Uncorrectable Multiple Bit Error L H H Read Valid Data Out X H H X Device Ready X H L X Device Ready / Scrub Request Pending X L X Not Accessible Device B
30、usy Note : L=low, H=high, X= dont care, Z=high impedance FIGURE 3. Truth table. G W E1 through E8 1/ I/O Mode Mode X X H DQ(31:0) Three-state Standby X L L DQ(31:0) Data in Write H H L DQ(31:0) Three-state Word Read (device active, outputs disabled) L H L DQ(31:0) Data out Word Read Provided by IHSN
31、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 18 DSCC FORM 2234 APR 97 Note: 50 pF including scope probe and test socket. FIGURE 4. Output load cir
32、cuit Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 19 DSCC FORM 2234 APR 97 Note: En and G VIL(max) and W VIH(min), only one En may
33、 be active at any given time. SRAM read cycle 1: Address Access Notes: 1. G VIL(max) and W VIH(min), only one En may be active at any given time. 2. SCRUB VOH(min) 3. Reading uninitialized addresses will cause MBE to be asserted. SRAM read cycle 2: Chip enable Access FIGURE 5. Timing waveforms. Prov
34、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 20 DSCC FORM 2234 APR 97 Notes: 1. En VIL(max) and W VIH(min) 2. SCRUB VOH(min) 3. Readin
35、g uninitialized addresses will cause MBE to be asserted. SRAM read cycle 3: Output Enable Access FIGURE 5. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARI
36、TIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 21 DSCC FORM 2234 APR 97 Notes: 1. G VIL(max) (If G VIH(min) then Q(31:0) and MBE will be three-state for the entire cycle) 2. SCRUB VOH(min) SRAM write cycle 1: W - controlled Access FIGURE 5. Timing waveforms - Continued. Provided by IHSNot for R
37、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 22 DSCC FORM 2234 APR 97 Notes: 1. G VIL(max) (If G VIH(min) then Q(31:0) and MBE will be three-state for the
38、 entire cycle) 2. SCRUB VOH(min) SRAM write cycle 2: Enabled - controlled Access FIGURE 5. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, O
39、HIO 43218-3990 REVISION LEVEL SHEET 23 DSCC FORM 2234 APR 97 Notes: 1. MBE is driven high by the user. 2. An address transition to 70000h must occur coincident with, or subsequent to, MBE assertion. 3. Lower 10 bits of the last address are used to read or configure the control register. 4. SCRUB VOH
40、before the start of the configuration cycle. Ignore SCRUB during configuration cycle. EDAC Control register cycle (Odd die numbers) FIGURE 5. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING
41、SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 24 DSCC FORM 2234 APR 97 Notes: 1. MBE is driven high by the user. 2. An address transition to 20820h must occur coincident with, or subsequent to, MBE assertion. 3. Bits A2 and A1 are used to read or configure th
42、e control register. 4. SCRUB VOHbefore the start of the configuration cycle. Ignore SCRUB during configuration cycle. EDAC Control register cycle (Even die numbers) FIGURE 5. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
43、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 25 DSCC FORM 2234 APR 97 Note: The conditions pertain to both Read or Write. Master mode SCRUB cycle Note: The conditions pertain to both Read or Write. Slave mode SCRUB cycle FIGU
44、RE 5. Timing waveforms - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10204 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 26 DSCC FORM 2234 APR 97 E1, E3, E5, E7 Chip Enab
45、led EDAC Control Register A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 | | | | | | | | | | | | | | | | | | | | Scrub Rate Period (Default = 7h) | | | | | | BUSY to SCRUB (Default = Ah) | | | | | | EDAC Bypass (Default = 0h) | | Read / Write Control Register E1, E3, E5, E7 Chip Enabled EDAC Programming Configuratio
46、n table ADDR BIT PARAMETER VALUE FUNCTION A (0 3) Scrub Rate Period 1, 2, 33 15 Note: 0 -2 reserved As SCRUB rate changes from 0 15, then the interval between SCRUB cycles will change as follows: 3 = 0.6 s 8 = 13.0 s 12 = 205 s 4 = 1.0 s 9 = 25.8 s 13 = 410 s (see note 4) 5 = 1.8 s 10 = 51.4 s 14 =
47、819 s (see note 4) 6 = 3.4 s 11 = 102.6 s 15 = 1.64 ms (see note 4) 7 = 6.6 s A (4 7) BUSY to SCRUB 2, 3, 50 - 15 If BUSY changes from 0 15, then the interval tBLSLbetween SCRUB and BUSY will change as follows: 0 = 0 ns 6 = 300 ns 11 = 550 ns 1 = 50 ns 7 = 350 ns 12 = 600 ns 2 = 100 ns 8 = 400 ns 13 = 650 ns 3 = 150 ns 9 = 450 ns 14 = 700 ns 4 = 200 ns 10 = 500 ns 15 = 750 ns 5 = 250 ns A (8) Bypass EDAC Bit 6
