1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 16 17 18 19 20 21 REV STATUS REV OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAW
2、ING CHECKED BY Laura Leeper THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Charles F. Saffle MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4MEG X 39-BIT (160M), RADIATION-HARDENED, DUAL VOLTAGE SRAM, MULTICHIP MODULE DRAWING APPROVAL DATE 13-01-02 A
3、MSC N/A REVISION LEVEL SIZE A CAGE CODE 67268 5962-10207 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E144-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10207 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990
4、REVISION LEVEL SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part o
5、r Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R 10207 01 Q X A Federal RHA Device Device Case Lead stock class designator type class outline finish designat
6、or (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet th
7、e MIL-PRF-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 UT8R4M39 4M
8、X 39-bit rad-hard SRAM 25 ns 02 UT8R4M39 4M X 39-bit rad-hard SRAM with additional screening 1/ 25 ns 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certificat
9、ion and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 132 dual cavity quad flat pack 1.2.5 Lead finish. The lead finish shall be as specifie
10、d in MIL-PRF-38535 for classes Q and V. 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage range, (VDD1) . -0.3 V dc to +2.1 V dc Supply voltage range, (VDD2) . -0.3 V dc to +3.8 V dc Voltage range on any pin . -0.3 V dc to +3.8 V dc Input current, dc . + 10 mA Power dissipation permitted PD TC= 105
11、C 1.3 W 4/ Case temperature range, (TC) . -55C to +105C Storage temperature range, (TSTG) -65C to +150C Junction temperature, (TJ) . +150C Thermal resistance, junction-to-case, (JC): Case X 15C/W Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA
12、RD MICROCIRCUIT DRAWING SIZE A 5962-10207 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 3/ Supply voltage range, (VDD1) . +1.7 V dc to +2.0 V dc Supply voltage range, (VDD2) . +2.3 V dc to +3.6 V dc Supply voltage,
13、(VSS) . 0 V dc Input voltage, dc 0 V dc to VDD2Case operating temperature range, (TC) -55C to +105C 1.5 Radiation features Maximum total dose available (effective dose rate = 1 rads(Si)/s) 100 K rads(Si) 5/ Single event phenomenon (SEP): Effective linear energy transfer (LET) with no upsets (see 4.4
14、.4.3) . 0.8 MeV - cm2/mg 6/ Effective LET with no latch-up (see 4.4.4.2) 100 errors or 106ions/cm2. c. The flux shall be between 102and 105ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magn
15、itude. d. The particle range shall be 20 microns in silicon. e. The test temperature shall be +25C 10C for single event upset testing and at the maximum rated operating temperature +10C for single event latch-up testing. f. Bias conditions shall be defined by the manufacturer for latch-up measuremen
16、ts. g. Test four devices with zero failures. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10207 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 19 DSCC FORM 2234 APR 97 5. PACKAGING 5.
17、1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications,
18、and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.2 Configuration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record fo
19、r the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMDs are applicable to that sy
20、stem. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-0544. 6.4 Comments. Comments
21、 on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614)692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 So
22、urces of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. 6.7 Additional information. When
23、applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Occurrence of latch-up (SEP). Provided by IHSNot for ResaleNo reproduction or networking permitted without
24、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10207 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL SHEET 20 DSCC FORM 2234 APR 97 APPENDIX A Appendix A forms a part of SMD 5962-10207 FUNCTIONAL ALGORITHMS A.1 SCOPE A.1.1 Scope. Functional algorithms are test patterns
25、 which define the exact sequence of events used to verify proper operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of
26、 each manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be applied to the device in a topologically
27、pure fashion. This appendix is a mandatory part of the specification. The information contained herein is intended for compliance. A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix. A.3 ALGORITHMS A.3.1 Algorithm A (pattern 1). A.3.1.1 Checkerboard, checkerboard-bar. Step 1.
28、Load memory with a checkerboard data pattern by incrementing from location 0 to maximum. Step 2. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum. Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum. Step 4.
29、Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum. A.3.2 Algorithm B (pattern 2). A.3.2.1 March. Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all “0s“). Step 2. Read data in location 0. Step 3. W
30、rite complement data to location 0. Step 4. Read complement data in location 0. Step 5. Repeat steps 2 through 4 incrementing X-fast sequentially for each location in the array. Step 6. Read complement data in maximum address location. Step 7. Write data to maximum address location. Step 8. Read dat
31、a in maximum address location. Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array. Step 10. Read data in location 0. Step 11. Write complement data to location 0. Step 12. Read complement data in location 0. Step 13. Repeat steps 10 through 12 decrementi
32、ng X-fast sequentially for each location in the array. Step 14. Read complement data in maximum address location. Step 15. Write data to maximum address location. Step 16. Read data in maximum address location. Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in
33、 the array. Step 18. Read background data from memory, decrementing X-fast from maximum to minimum address locations. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-10207 DLA LAND AND MARITIME COLUMBUS, OHIO
34、 43218-3990 REVISION LEVEL SHEET 21 DSCC FORM 2234 APR 97 APPENDIX A - continued. Appendix A forms a part of SMD 5962-10207 A.3.3 Algorithm C (pattern 3). A.3.3.1 XY March. Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all “0s“). Step 2. Read data
35、in location 0. Step 3. Write complement data to location 0. Step 4. Read complement data in location 0. Step 5. Repeat steps 2 through 4 incrementing Y-fast sequentially for each location in the array. Step 6. Read complement data in maximum address location. Step 7. Write data to maximum address lo
36、cation. Step 8. Read data in maximum address location. Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array. Step 10. Read data in location 0. Step 11. Write complement data to location 0. Step 12. Read complement data in location 0. Step 13. Repeat steps
37、10 through 12 decrementing Y-fast sequentially for each location in the array. Step 14. Read complement data in maximum address location. Step 15. Write data to maximum address location. Step 16. Read data in maximum address location. Step 17. Repeat steps 14 through 16 incrementing X-fast sequentia
38、lly for each location in the array. Step 18. Read background data from memory, decrementing Y-fast from maximum to minimum address locations. A.3.4 Algorithm D (pattern 4). A.3.4.1 CEDES - CE deselect checkerboard, checkerboard-bar. Step 1. Load memory with a checkerboard data pattern by incrementin
39、g from location 0 to maximum. Step 2. Deselect device, attempt to load memory with checkerboard-bar data pattern by incrementing from location 0 to maximum. Step 3. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum. Step 4. Load memory with a checkerbo
40、ard-bar pattern by incrementing from location 0 to maximum. Step 5. Deselect device, attempt to load memory with checkerboard data pattern by incrementing from location 0 to maximum. Step 6. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum. Provid
41、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-01-02 Approved sources of supply for SMD 5962-10207 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535
42、 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is supe
43、rseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http:/www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962R1020701QXC 6534
44、2 UT8R4M39-25XFC 5962R1020702QXC 65342 UT8R4M39-25XFC 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution
45、. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE Vendor name number and address 65342 Aeroflex Colorado Springs, Inc. 4350 Centennial Blvd. Colorado Springs, CO 80907-7370 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-
