1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Made changes to table I and editorial changes throughout. Changed PDA from 10 percent to 5 percent. 91-03-06 M. A. Frye B Changes in accordance with NOR 5962-R196-92. 92-11-02 M. A. Frye C Incorporate revision B NOR. Update drawing to current req
2、uirements. Editorial changes throughout. - drw 05-12-16 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. CURRENT CAGE CODE 67268 REV SHET REV SHET REV STATUS REV C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 PMIC N/A PREPARED BY Gary Zahn DEFENSE SUPPLY CENTER COLUMBUS ST
3、ANDARD MICROCIRCUIT DRAWING CHECKED BY William E. Shoup COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY N. A. Hauck MICROCIRCUIT, LINEAR, 12-BIT D/A CONVERTER, RANGE PROGRAMMABLE, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPR
4、OVAL DATE 83-10-04 VOLTAGE OUTPUT, MONOLITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 14933 83003 SHEET 1 OF 8 DSCC FORM 2233 APR 97 5962-E151-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DE
5、FENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Nu
6、mber (PIN). The complete PIN is as shown in the following example: 83003 01 J A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type. The device type identifies the circuit function as follows: Device type Generic number Circuit function 01 DAC87 D/A
7、 converter, 12-bit with voltage Ranges as follows: 0 V to +5 V unipolar 0 V to +10 V unipolar -2.5 V to +2.5 V bipolar -5 V to +5 V bipolar -10 V to +10 V bipolar 1.2.2 Case outline. The case outline is as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package
8、 style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Positive supply voltage VCCto digital return. +18 V dc Negative supply voltage VEEto digital return -18 V dc Digital input voltage to digital
9、 return. 0 V dc to 7.0 V dc Output short circuit duration (to ground only). 25 ms Lead temperature (soldering, 60 seconds) +300C Storage temperature range -65C to +150C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 Thermal resistance, junction-to-ambient
10、 (JA) 48C/W Power dissipation (PD) 1/ . 550 mW 1.4 Recommended operating conditions. Positive supply voltage (VCC) . +16.5 V dc Negative supply voltage (VEE) -16.5 V dc Ambient operating temperature range (TA) -55C to +125C _ 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provid
11、ed by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standar
12、ds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrat
13、ed Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HD
14、BK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In
15、the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The
16、 individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been
17、granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to
18、the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Desig
19、n, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as s
20、pecified on figure 1. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test require
21、ments shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be
22、marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the
23、 QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performan
24、ce characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxResolution 12 Bits Supply current from VCCICCInput bits = 1111 1111 1111, VCC= 15 V 1, 2, 3 01 1 10 mA Supply current from VEEIEEInput bits = 0000 0000 0000, VCC= -
25、15 V 1, 2, 3 01 -20 -1 mA Digital input low current IILVIN= 0.8 V, VCC= 15 V, (each input measured separately) 1, 2, 3 01 0 +100 A Digital input high current IIHVIN= 5.5 V, VCC= 15 V 1, 2, 3 01 -1 +250 A Output short circuit current IOSInput bits = 0000 0000 0000 1, 2, 3 01 40 mA Reference voltage V
26、REFIO= -2.5 mA, TA= +25C 1 01 6.23 6.37 V Reference voltage drift dVREF/ dT 2/ 2, 3 01 -10 +10 PPM/C Unipolar offset voltage error VOSInput bits = 1111 1111 1111, Unipolar, VFSR= 10 V, TA= +25C 1 01 -0.1 +0.1 % FSR Unipolar offset voltage drift dVOS/ dT 2/ 2, 3 01 -3 +3 PPM/C Gain error 3/ AE Input
27、bits = 0000 0000 0000, Input bits = 1111 1111 1111, Unipolar, VFSR= 10 V, TA= +25C 1 01 -0.2 +0.2 % FSR Gain error drift dAE/dT 2/ 2, 3 01 -20 +20 PPM/C Bipolar gain error 4/ BPAE Input bits = 0000 0000 0000, Input bits = 1111 1111 1111, TA= +25C 1 01 -0.2 +0.2 % FSR Bipolar offset error 4/ BPOE Inp
28、ut bits = 1111 1111 1111, TA= +25C 1 01 -0.1 +0.1 % FSR Bipolar offset error drift dBPOE/ dT 2/ 2, 3 01 -10 +10 PPM/C Bipolar zero error 4/ BZE Input bits = 0111 1111 1111, TA= +25C 1 01 -4 +4 LSB Bipolar zero error drift dBZE/ dT 2/ 2, 3 01 -10 +10 PPM/C Power supply sensitivity from VCCat full sca
29、le +PSRR Input bits = 0000 0000 0000, +13.5 V VCC +16.5 V, +11.4 V VCC +12.6V, VEE= -15 V, VEE= -12 V 1, 2, 3 01 -0.002 +0.002 %FSR %VCCPower supply sensitivity from VEEat full scale -PSRR Input bits = 0000 0000 0000, -13.5 V VCC -16.5 V, -12.6 V VCC -11.4 V, VCC= +15 V, VCC= +12 V 1, 2, 3 01 -0.002
30、 +0.002 %FSR %VEESee footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I.
31、 Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxIntegral linearity error LE (Abbreviate codes test) 5/ 1 01 -0.5 +0.5 LSB 2, 3 -0.75 +0.75 Differential linearity error DLE (Abbrev
32、iate codes test) 1 01 -0.75 +0.75 LSB 2, 3 -1.0 +1.0 Integral linearity error LE (All codes test) 7 01 -0.5 +0.5 LSB 8 -0.75 +0.75 Settling time 6/ tSLH20 V to 1/2 LSB 9 01 5 s TA= +25C 20 V to 1 LSB 4 Input bits = 1111 1111 1111 to input bits = 0000 0000 0000 1 LSB to 1/2 LSB, TA= +25C Input bits =
33、 1111 1111 1111 to input bits = 1111 1111 1110 2 Settling time 6/ tSHL20 V to 1/2 LSB 9 01 5 s TA= +25C 20 V to 1 LSB 4 Input bits = 0000 0000 0000 to input bits = 1111 1111 1111 1 LSB to 1/2 LSB, TA= +25C Input bits = 1111 1111 1110 to input bits = 1111 1111 1111 2 Output noise voltage 6/ NO All in
34、puts = 1111 1111 1111, 10 Hz 8W 100 kHz, TA= +25C 9 160 V rms 1/ Unless otherwise specified, VCC= 15.0 V, VEE= -15.0 V, logic “0” = 0.8 V, logic “1” = 2.0 V, VFSR= 10 V, and load resistance (RL) = 2k. This is a unipolar operation. Load resistor (RL) not applicable for ICCand IEEtest. 2/ Calculations
35、 for dVOS/dT, dAE/dT, dBPOE/dT, dBZE/dT, and dVREF/dT are determined from measurements made at +125C, +25C, and -55C for VOS, AE, BPOE, BZE, and VREFrespectively. 3/ The gain error of a 12 bit D/A converter in % of full scale range corresponds to gain error in LSB units by the following relationship
36、: 0.20% x 4096 LSB/100% = 8.192 LSB. 4/ Test bipolar mode over a -10 V to +10 V range. The scale factor is VFSR/4096 LSB. (i.e. For VFSR= 20 V, the scale factor is 20 V/4096 LSB = 4.88 mV/LSB.) 5/ The abbreviated integral linearity error test shown for subgroups 1, 2, and 3 shall represent the minim
37、um number of tests required. The manufacturer shall add additional tests and/or calculations to assure that the worst positive and negative error values, as determined by the abbreviated test, are within 150 milli LSB of the worst positive and negative error values, as determined by the all codes te
38、st for subgroups 7 and 8. 6/ If not tested, shall be guaranteed to the limits specified in table I herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-
39、3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Device type 01 Case outline J Terminal number Terminal symbol 1 BIT 1 (MSB) 2 BIT 2 3 BIT 3 4 BIT 4 5 BIT 5 6 BIT 6 7 BIT 7 8 BIT 8 9 BIT 9 10 BIT 10 11 BIT 11 12 BIT 12 (LSB) 13 LOGIC SUPPLY 14 VEE15 VOUT16 REF INPUT17 BIPOLAR OFFSET 18 10 V RANGE
40、 19 20 V RANGE 20 SUMMING JUNCTION 21 COMMON 22 VCC23 GAIN ADJUST 24 6.3 VREFOUT FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 83003 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO
41、43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior
42、to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lo
43、t of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility an
44、d applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accor
45、dance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition B, C, or D. The test circuit shall be maintained by the manufacturer un
46、der document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C,
47、 minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance
48、 with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, 6, 10, and 11 in table I, method 5005 of MIL-STD-883 shall be omitted. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition B, C, or D. The test circuit shall
