1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Outline letter, Y, case outline changed to F-11 for standardization. Convert to military drawing format. Editorial changes throughout. 88-01-19 Michael A. Frye B Make change to table I, table II, 1.2. 2, 3. 3, and 4.3. Add figure 5. Editorial cha
2、nges throughout. Make change to figure 4. 89-04-04 Michael A. Frye C Updated boilerplate. Added device type 02. Removed CAGE 34335 from drawing and added CAGE 0DKS7. - glg 99-10-19 Raymond Monnin D Added provisions for the addition of QD certified parts to drawing. Added CAGE OC7V7 as supplier. - gl
3、g 00-02-03 Raymond Monnin E Corrected marking paragraph 3.5, updated boilerplate paragraphs. ksr 05-04-01 Raymond Monnin F Updated body of drawing to reflect current requirements. - glg11-03-08 Charles Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED CURRENT CAGE CODE 67268 REV SHET
4、REV F F SHET 15 16 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY D. A. DiCenzo THIS DRAWING IS AVAILABLE FO
5、R USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Nelson Hauck MICROCIRCUITS, MEMORY, DIGITAL, BIPOLAR, 16-WORD BY 4-BIT, 2-PORT, RAM, MONOLITHIC SILICON DRAWING APPROVAL DATE 31 MARCH 1986 REVISION LEVEL F SIZE A CAGE CODE 14933 86025 AMSC N/A SHEET 1 OF 16 DSCC FORM 22
6、33 APR 97 5962-E188-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describ
7、es device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 86025 01 X X Drawing number Device type Case outline Lead finish (see 1.2.1
8、) (see 1.2.2) (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit 01 29705A 16-word by 4-bit, 2-port RAM, 30 ns 02 29705A-35 16-word by 4-bit, 2-port RAM, 35 ns 1.2.2 Case outline(s). The case outline(s) are as designated
9、in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 dual-in-line package Y GDFP2-F28 28 flat package 3 CQCC1-N28 28 square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 A
10、bsolute maximum ratings. Storage temperature -65C to +150C Supply voltage to ground potential . -0.5 V dc to +7.0 V dc DC voltage applied to outputs for high output stage -0.5 V dc to +VCCmaximum DC input voltage -0.5 V dc to +5.5 V dc DC output current, into outputs 30 mA DC input current -30 mA to
11、 +5.0 mA Maximum power dissipation (PD) 1/ . 1.155 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC): See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage (VCC) +4.5 V dc to +5.5 V dc Minimum high level inpu
12、t voltage (VIH) . +2.0 V dc Maximum low level input voltage (VIL) +0.8 V dc Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards and handbooks form a part of this drawing to the ex
13、tent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN
14、DARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test
15、Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.
16、daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. N
17、othing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
18、 herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved prog
19、ram plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affe
20、ct the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-3853
21、5 or other alternative approved by the qualifying activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified o
22、n figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.3 Electrical performance characteristics. Unless otherwise sp
23、ecified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgro
24、up are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked
25、on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of MIL-PRF-38535,
26、 or as modified in the manufacturers QM plan, the “QD” certification mark shall be used in place of the “Q“ or “QML“ certification mark. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME
27、COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups Limits Unit Min Max Output high voltage VOHVCC= minimum, IOH= -2.
28、0 mA VIN= VIHor VILAll 1, 2, 3 2.4 V Output low voltage VOLVCC= minimum, IOL= 16 mA VIN= VIHor VILAll 1, 2, 3 0.5 V Input high level VIHGuaranteed input logical high voltage for all inputs All 1, 2, 3 2 V Input low level VILGuaranteed input logical low voltage for all inputs All 1, 2, 3 0.8 V Input
29、clamp voltage VIVCC= minimum, IIN= - 18 mA All 1, 2, 3 -1.5 V Input low current IILVCC= maximum, VIN= 0.5 V All 1, 2, 3 -0.36 mAInput high current IIHVCC= maximum, VIN= 2.7 V All 1, 2, 3 20 A IIVCC= maximum, VIN= 5.5 V All 1, 2, 3 0.1 mA Off state (high impedance) output current IOVCC= maximum VIN=
30、VIHor VILVO= 2.4 V All 1, 2, 3 20 A VO= 0.5 V -20 Output short circuit current 1/ IOSVCCmaximum + .5 V, VO= 0.5 V All 1, 2, 3 -30 -85 mA Power supply current ICCVCC= maximum (Worst case ICCis at minimum temperature) 2/ TC= -55C to +125C All 1, 2, 3 210 mA TC= +125C 150 Functional tests See 4.3.1c Al
31、l 7,8A,8B See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical per
32、formance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specifiedDevicetypes Group A subgroups Limits Unit Min Max Access time from: A address stable or B address stable to: YA stable or YB stable tAASee figure 4 and 5 CL= 50 pF, LE = high 01 9,
33、10, 11 30 ns 02 35 Turn-on time from: AOE or BOE low to: YA or YB stable tONSee figure 4 and 5 CL= 50 pF All 9, 10, 11 20 ns Turn-off time from: AOE or BOE high to: YA or YB off tOFFSee figure 4 and 5 CL= 5 pF 3/ All 9, 10, 11 20 ns Reset time from: LOA low to: YA low tRESSee figure 4 and 5 CL= 50 p
34、F All 9, 10, 11 20 ns Latch enable time from: LE high to: YA and YB stable tENSee figure 4 and 5 CL= 50 pF 01 9, 10, 11 22 ns 02 30 Transparency 1 from: WE1and WE2low to: YA or YB tPD1See figure 4 and 5 CL= 50 pF, LE = high 01 9, 10, 11 35 ns 02 40 Transparency 2 from: D to: YA or YB tPD2See figure
35、4 and 5 CL= 50 pF, LE = high 01 9, 10, 11 35 ns 02 40 Data setup time from: D stable to: Either WE high tS1See figure 4 and 5 CL= 50 pF All 9, 10, 11 15 ns Data hold time from: Either WE high to: D changing tH1See figure 4 and 5 CL= 50 pF All 9, 10, 11 0 ns See footnotes at end of table. Provided by
36、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Co
37、nditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups Limits Unit Min MaxAddress setup time from: B stable to: Both WE low tS2See figure 4 and 5 CL= 50 pF All 9, 10, 11 8 ns Address hold time from: Either WE high to: B changing tH2See figure 4 and 5 CL= 5
38、0 pF All 9, 10, 11 0 ns Latch close before write begin 1 from: LE low to: WE1 low tPD3CL= 50 pF, WE2low See figure 4 and 5 All 9, 10, 11 0 ns Latch close before write begin 2 from: LE low to: WE2 low tPD4CL= 50 pF, WE1 low See figure 4 and 5 All 9, 10, 11 0 ns Address set up before latch closes from
39、: A or B stable to : LE low tS3See figure 4 and 5 CL= 50 pF All 9, 10, 11 15 ns Write pulse width 1 Input: WE , Pulse: High-low-high tPW1CL= 50 pF, WE2 low See figure 4 and 5 All 9, 10, 11 15 ns Write pulse width 2 Input: WE2, Pulse: High-low-high tPW2CL= 50 pF, WE1 low See figure 4 and 5 All 9, 10,
40、 11 15 ns A latch reset pulse Input: LOA , Pulse: High-low-high tPW3See figure 4 and 5 CL= 50 pF All 9, 10, 11 15 ns Latch data capture Input: LE Pulse: Low-high-low tPW4See figure 4 and 5 CL= 50 pF All 9, 10, 11 18 ns 1/ Not more than one output should be shorted at a time. Duration of the sort cir
41、cuit test should not exceed 1 second. 2/ All inputs grounded except AOE and BOE = 2.4 V 3/ Measured from 1.5V at the input to 0.5V change in the output level. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025
42、DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 Device type All Case outline X, Y, 3 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 D1D0WE1B0B1B2B3LOA LE YB0YA0YB1YA1GND YB2YA2YB3YA3BOE AOE A3A
43、2A1A0WE2D3D2VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 8 DSCC FORM 2234 APR 97 Write control WE1
44、 WE2 Function RAM outputs at latch inputs A-port B-port L L X H L L H X Write D into B Write D into B No write No write A data (A B) (A = B) Input dataA data A data Input data Input data B data B data H = High L = Low X = Dont care YA READ Inputs YA output Function AOE LOA LE H L L L X L H H X X H L
45、 Z L A-port RAM data NC High impedance Force YA low Latches transparent Latches retain data H = High X = Dont care NC = No Change L = Low Z = High impedance YB READ Inputs YB output Function BOE LE H L L X H L Z B-port RAM dataNC High impedance Latches transparent Latches retain data H = High X = Do
46、nt care NC = No Change L = Low Z = High impedance FIGURE 2. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 9 DSCC FORM 22
47、34 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 86025 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 10 DSCC FORM 2234 APR 97 THREE-STATE OUTPUT 5.0 - VBE- VOLR1= IOL+ VOL/1K NOTES: 1. CL= 50 pF includes scope probe, wiring and stray capacitances without device in text fixture. 2. S1, S2, and S3are closed during function tests and all ac tests except out
