1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - drw 05-08-16 Raymond Monnin THE FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11
2、PMIC N/A PREPARED BY Rick C Officer DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles E. Besore COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, ELECTROLUMINESCENT COL
3、UMN DRIVER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-01-02 MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-86055 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E380-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license fr
4、om IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordan
5、ce with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86055 01 X A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device types. The device types identify the circuit function as
6、 follows: Device type Generic number Circuit function 01 55553 Electroluminescent column driver (see figures 1 and 5) 02 55554 Electroluminescent column driver (see figures 1 and 5) 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive de
7、signator Terminals Package style X CQCC1-N44 44 square leadless chip carrier Y CQCC2-J44 44 J-lead chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ Supply voltage 1 (VCC1) 18 V dc Supply voltage 2 (VCC2) 70 V dc Input volt
8、age -0.3 V dc to VCC1+ 0.3 V dc GND current 70 mA Storage temperature -65C to +150C Lead temperature (soldering, 10 seconds) +300C Power dissipation (PD) . 1475 mW 2/ Junction temperature (TJ) 150C Thermal resistance, junction-to-case (JC). See MIL-STD-1835 1.4 Recommended operating conditions. Supp
9、ly voltage 1 (VCC1) 10.8 V dc to 13.2 V dc Supply voltage 2 (VCC2) 0 V dc to 60 V dc High level input voltage: VCC1= 10.8 V . 8.1 V dc minimum VCC1= 13.2 V . 9.9 V dc minimum Low level input voltage: VCC1= 10.8 V . 2.7 V dc maximum VCC1= 13.2 V . 3.3 V dc maximum High level output current (IOH) -15
10、mA maximum Low level output current (IOL) . 15 mA minimum Output clamp current (IOK) . 20 mA maximum Clock frequency (fCLK) (TA= +25C). 6.25 MHz Ambient operating temperature range (TA) -55C to +125C _ 1/ All voltages are referenced to GND. 2/ 1475 mW for operation between -55C to +125C. For operati
11、ng above +25C free-air temperature, derate linearly at 14.6 mW/C.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FO
12、RM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitati
13、on or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEF
14、ENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Ave
15、nue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a spec
16、ific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listin
17、g (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow
18、as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-P
19、RF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.
20、2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless other
21、wise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for e
22、ach subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. El
23、ectrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C VCC1= 12 V, VCC2= 60 V, GND = 0 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Supply current from VCC1ICC1Outputs open 1, 2, 3 All 7 mA Supply current from VCC2ICC2Outputs high 1, 2, 3 All
24、20 mA Outputs low 2 Low level input current IILVI= 0 V 2/ 1, 2, 3 All -5 A High level input current IIHVI= 0 V 2/ 1, 2, 3 All 5 A High level output voltage, Q outputs VOHQIO= -15 mA 1, 2, 3 All 55 V Low level output voltage, Q outputs VOLQIO= 15 mA 1, 2, 3 All 10 V High level output voltage, serial
25、output VOHSIO= -100 A 1, 2, 3 All 10 V Low level output voltage, serial output VOLSIO= 100 A 1, 2, 3 All 1.5 V Functional tests See 4.3.1c 7, 8 All Clock frequency fCLKTA= +25C 9 All 6.25 MHz Propagation delay time, low to high level, Q outputs tPLHSee figure 3, TA= +25C 9 All 1000 ns Propagation de
26、lay time, high to low level, Q outputs tPLHSee figure 3, TA= +25C 9 All 700 ns Data hold time after rising clock tHSee figure 3, TA= +25C 9 All 110 ns Delay time, high to low level, serial output from clock tDHLCL= 45 pF to ground, see figure 3, TA= +25C 9 All 200 ns Delay time, low to high level, s
27、erial output from clock tDLHCL= 45 pF to ground, see figure 3, TA= +25C 9 All 200 ns Clock pulse duration, high or low tWSee figure 3, TA= +25C 9 All 80 ns Data setup time, before rising clock tSUSee figure 3, TA= +25C 9 All 50 ns 1/ Voltage measured with respect to GND unless otherwise noted. 2/ II
28、Land IIHparameter performances are independent of VCC2which need not be 60 V for this test. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVIS
29、ION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 Device types 01 02 Case outlines X and Y X and Y Terminal number Terminal symbol 1 Q17 Q16 2 Q16 Q17 3 Q15 Q18 4 Q14 Q19 5 Q13 Q20 6 Q12 Q21 7 Q11 Q22 8 Q10 Q23 9 Q9 Q24 10 Q8 Q25 11 Q7 Q26 12 Q6 Q27 13 Q5 Q28 14 Q4 Q29 15 Q3 Q30 16 Q2 Q31 17 Q1 Q32 18 DATA
30、OUT DATA OUT 19 NC NC 20 NC NC 21 NC NC 22 CLOCK CLOCK 23 GND GND 24 VCC2VCC225 VCC1 CC126 LATCH ENABLE LATCH ENABLE 27 DATA IN DATA IN 28 OUTPUT ENABLE OUTPUT ENABLE 29 NC NC 30 Q32 Q1 31 Q31 Q2 32 Q30 Q3 33 Q29 Q4 34 Q28 Q5 35 Q27 Q6 36 Q26 Q7 37 Q25 Q8 38 Q24 Q9 39 Q23 Q10 40 Q22 Q11 41 Q21 Q12 4
31、2 Q20 Q13 43 Q19 Q14 44 Q18 Q15 FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FOR
32、M 2234 APR 97 Control inputs Outputs Function Clock Latch enable Output enable Shift register R1 thru R32 Latches LC1 thru LC32 Serial Q1 thru Q32 X X Load and shift 1/ Determined by latch enable 2/ R32 Determined by output enable Load No X X No Change Determined by latch enable 2/ R32 Determined by
33、 output enable X L X As determined above Stored data R32 Determined by output enable Latch X H X As determined above New data R32 Determined by output enable X X L As determined above Determined by latch enable 2/ R32 All L Output enable X X H As determined above Determined by latch enable 2/ R32 LC
34、1 thru LC32 respectively H = HIGH level, L = LOW level, X = Irrelevant, = LOW-to-HIGH level transition. 1/ R32 and the serial output take on the state of R31, R31 takes on the state of R30R32 takes on the state of R1, and R1 takes on the state of the data input. 2/ New data enter the latches while l
35、atch enable is high. These data are stored while latch enable is low. FIGURE 2. Truth table and logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OH
36、IO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 INPUT TIMING WAVEFORMS WAVEFORMS FOR DELAY AND TRANSITION TIMES, CLOCK TO SERIAL OUTPUT FIGURE 3. Timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRA
37、WING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 WAVEFORMS FOR PROPAGATION DELAY TIMES, LATCH ENABLE TO Q OUTPUTS FIGURE 3. Timing waveforms continued. Provided by IHSNot for ResaleNo reproduction or networking permitted w
38、ithout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
39、 in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicat
40、or “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certif
41、icate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the
42、requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change
43、to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at th
44、e option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality con
45、formance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring
46、activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II he
47、rein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86055 DEFENSE SUPPLY CENTER COLUMBUS COLUMB
48、US, OHIO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - - - Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9 Group A test requirements (method 5005) 1, 2, 3, 7, 8, 9 Groups C and D end-point electrical parameters (method 5005) 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection
