1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Change transition indicators on page 5. Change footnote 2 on table II. 87-09-16 N. A. Hauck B Separate subgroup 9 from subgroups 10 and 11 on page 5. Table I, SRCLR change arrow to pointing downward on page 5. Editorial changes throughout. Add fi
2、gure 4. 88-03-15 M. A. Frye C NOR 5962-R126-92. Revisions to Table I and Figure 4. - tvn 92-02-05 Monica L. Poelking D Update to reflect latest changes in format and requirements. Editorial changes throughout. - les 02-06-20 Raymond Monnin E Update drawing to current requirements. Editorial changes
3、throughout. - gap 09-06-24 Charles F. Saffle Current CAGE code is 67268 The original first sheet of this drawing has been replaced. REV SHET REV SHET REV STATUS REV E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY David W. Queenan DEFENSE SUPPLY CENTER COL
4、UMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY D. A. DiCenzo APPROVED BY N. A. Hauch MICROCIRCUIT, DIGITAL, LOW POWER SCHOTTKY, TTL, 8-BIT SHIFT REGISTER, M
5、ONOLITHIC SILICON DRAWING APPROVAL DATE 87-02-25 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 14933 5962-86717 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E120-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86
6、717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identify
7、ing Number (PIN). The complete PIN is as shown in the following example: 5962-86717 01 E X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit functi
8、on 01 54LS595 8-Bit shift register with three-state outputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line package F GDFP2-F16 or CDFP3-F16 16 Flat pac
9、kage 2 CQCC1-N20 20 Square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage . -0.5 V dc to +7.0 V dc Input voltage range . -1.5 V dc at -18mA to +7.0 V dc Off-state output voltage . +5.5 V Lead temperature (sol
10、dering, 10 seconds) +300C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Storage temperature range -65C to +150C Maximum power dissipation (PD) 1/ 358 mW 1/ 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Minimum
11、 high level input voltage (VIH) 2.0 V dc Maximum low level input voltage (VIL) . 0.7 V dc Maximum high level output current (IOH) . -1.0 mA Maximum low level output current (IOL): QHoutput . 8 mA Q output . 12 mA _ 1/ Must withstand the added PDdue to short circuit test (e.g. IOS). Provided by IHSNo
12、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 Shift clock frequency . 0 MHz to 20 MHz Minimum duration of : Shift
13、 clock pulse . 25 ns Register clock pulse . 20 ns Shift clear pulse, low level 20 ns Minimum setup time (tSU): SRCLR 20 ns SER before SRCK . 20 ns SRCK before RCK 2/ 40 ns SRCLR low before RCK 40 ns Minimum hold time (th) 0 ns Case operating temperature (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1
14、 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPEC
15、IFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Stan
16、dard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence
17、. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 2/ This setup time ensures the regi
18、ster will see stable data from the shift-register outputs. The clocks may be connected together, in which case the storage register state will be one clock pulse behind the shift register. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR
19、OCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices a
20、nd as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturer
21、s approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications
22、 shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MI
23、L-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The
24、logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as sp
25、ecified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accord
26、ance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the
27、 “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to i
28、dentify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an
29、 approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircui
30、ts delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable req
31、uired documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4
32、3218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C Group A subgroups Limits Unit unless otherwise specified Min Max Input clamp voltage VI CVCC= 4.5 V, IIH= -18 mA 1 -1.5 V High level output voltage VOH VCC= 4
33、.5 V, IOH= -1.0 mA, VIN= 0.7 V or 2.0 V 1, 2, 3 2.4 V Low level output voltage at Q outputs VOL1 VCC= 4.5 V, IOL= 12 mA, VIN= 2.0 V or 0.7 V 1, 2, 3 0.4 V Low level output voltage at QHoutput VOL2 VCC= 4.5 V, IOL= 8.0 mA, VIN= 0.7 V or 2.0 V, 1, 2, 3 0.4 V High impedance state output current IOZHVCC
34、= 5.5 V, VOH= 2.7 V, VIN= 0.7 V or 2.0 V 1, 2, 3 20 A IOZLVCC= 5.5 V, VOH= 0.4 V, VIN= 0.7 V or 2.0 V 1, 2, 3 -20 A High level input current II H1 VCC= 5.5 V, VIN= 7.0 V 1, 2, 3 0.1 mA II H2 VCC= 5.5 V, VIN= 2.7 V 1, 2, 3 20 A Low level input current IILVCC= 5.5 V, VIN= 0.4 V SER input 1, 2, 3 -0.4
35、mA Other inputs 1, 2, 3 -0.2 mA Short circuit output current IOS VCC= 5.5 V, VOUT= 0 V 1/ Q outputs 1, 2, 3 -30 -130 mA QHoutput 1, 2, 3 -20 -100 mA Supply current ICCH VCC= 5.5 V, all possible inputs grounded, all outputs open 1, 2, 3 50 mA ICCL 1, 2, 3 65 mA ICCZ 1, 2, 3 65 mA Functional tests See
36、 4.3.1c 7, 8 Propagation delay time, tPLH1 VCC= 5.0 V, RL= 1 k 5%, CL= 30 pF 10% See figure 4. 9 18 ns SRCK to QH10, 11 25 ns tPHL1 9 25 ns 10, 11 35 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC
37、UIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC+125C Group A subgroups Limits Unit unless otherwise specified Min Max Propagation dela
38、y time, RCK to Q tPLH2 VCC= 5.0 V, RL= 667 5%, CL= 45 pF 10% See figure 4. 9 18 ns 10, 11 25 ns tPHL2 9 35 ns 10, 11 49 ns Propagation delay time, G to Q tPZH9 30 ns 10, 11 50 ns tPZL9 38 ns 10, 11 53 ns Propagation delay time, G to Q tPHZVCC= 5.0 V, RL= 667 5%, CL= 5 pF 10% See figure 4. 9 30 ns 10
39、, 11 42 ns tPLZ9 38 ns 10, 11 53 ns Propagation delay time, SRCLR to QHtPHL3 VCC= 5.0 V, RL= 1 k 5%, CL= 30 pF 10% See figure 4. 9 35 ns 10, 11 49 ns 1/ Not more than one output should be shorted at one time and the duration of the short circuit condition should not exceed one second. Provided by IH
40、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal number Terminal
41、symbols 1 QBNC 2 QCQB3 QDQC4 QEQD5 QFQE6 QGNC 7 QHQF8 GND QG9 QHQH10 SRCLR GND 11 SRCK NC12 RCK QH13 GSRCLR 14 SER SRCK15 QARCK16 VCCNC 17 G 18 SER 19 QA20 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI
42、CROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 8 DSCC FORM 2234 APR 97 Inputs SRCLR SER SRCK RCK G Resulting function L X X X X Shift register contents are cleared. H L X X A low logic level is shifted into the shift register. H H
43、 X X A high logic level is shifted into the shift register. H X X X Shift register remains unchanged. H X L X Shift register data stored in the 8-bit latch. H X L X Date latch remains unchanged. H X L L L Latch outputs, QA- QH, are enabled. H X L L H Outputs QA- QHare in the high impedance state. FI
44、GURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Prov
45、ided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 10 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms. Provided by IHSNot for
46、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 11 DSCC FORM 2234 APR 97 FIGURE 4. Switching waveforms - Continued. Provided by IHSNot for Resal
47、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86717 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 12 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedur
48、es shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A or D. The test circuit shall be maintained by the manufacturer under document revision
