DLA SMD-5962-86831 REV C-2013 MICROCIRCUIT DIGITAL HIGH-SPEED CMOS QUAD 2-INPUT NAND GATE WITH TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes are in accordance with the notice of revision 5962-R058-95. - tvn 95-01-31 Monica L. Poelking B Correct the title to accurately describe the device function. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Ed

2、itorial changes throughout. jak 07-01-22 Thomas M. Hess C Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 13-06-21 Thomas M. Hess Current CAGE CODE is 67268 REV SHEET REV SHEET REV STATUS REV C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY

3、 Greg A. Pitz DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Daniel A. DiCenzo APPROVED BY Nelson A. Hauck MICROCIRCUIT,

4、 DIGITAL, HIGH-SPEED CMOS, QUAD 2-INPUT NAND GATE WITH TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 87-02-26 REVISION LEVEL C SIZE A CAGE CODE 14933 5962-86831 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E448-13 Provided by IHSNot for ResaleNo reproduction or networking permitted wit

5、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in ac

6、cordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86831 01 C A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circui

7、t function as follows: Device type Generic number Circuit function 01 54HCT00 Quad 2-input NAND gate with TTL compatible inputs 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CD

8、IP2-T14 14 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC + 0.5 V dc DC output voltage range (VOUT) -0.5 V dc to VCC+

9、 0.5 V dc Clamp diode current (IIK), (IOK) 20 mA DC output current (IOUT) (per pin) 25 mA DC VCCor GND current (ICC, IGND) (per pin) 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) 500 mW 3/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junc

10、tion-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Case operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf) (VCC= 4.5 V) . 0 to 500 ns 1/ Stresses above the absolut

11、e maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for Resa

12、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The fo

13、llowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturin

14、g, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microci

15、rcuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). 2.2 Non-Government publications. The following document(s) form a part of this document to the

16、extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents a

17、re available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201-2107). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing ta

18、kes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices

19、 and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufactur

20、ers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modificatio

21、ns shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

22、MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. Provided by IHSNot for Re

23、saleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Swit

24、ching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case opera

25、ting temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be mark

26、ed with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark

27、. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate o

28、f compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm t

29、hat the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notific

30、ation of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and app

31、licable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO

32、 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified VCCGroup A subgroups Limits Unit Min Max High level output voltage VOHVIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 4.5 V 1,

33、2, 3 4.4 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -4.0 mA 4.5 V 3.7 Low level output voltage VOLVIN= VIH= 2.0 V or VIL= 0.8 V IOL= +20 A 4.5 V 1, 2, 3 0.1 V VIN= VIH= 2.0 V or VIL= 0.8 V IOL= +4.0 mA 4.5 V 0.4 High level input voltage VIH4.5 V 1, 2, 3 2.0 V Low level input voltage VIL4.5 V 1, 2, 3 0.8 V

34、 Input capacitance CINVIN= 0 V TC= +25C See 4.3.1c 4 10 pF Quiescent current ICCVIN= VCCor GND IOUT= 0 A 5.5 V 1, 2, 3 40 A Additional quiescent supply current ICCAny one input, VIN= 3.4 V Other inputs, VIN= VCCor GND IOUT= 0 A 4.5 V to 5.5 V 1, 2, 3 890 A Input leakage current IINVIN= VCCor GND VIN

35、= VIH= 2.0 V or VIL= 0.8 V 5.5 V 1, 2, 3 1 A Functional tests See 4.3.1d 7 Propagation delay time, high-to-low low-to-high tPHL, tPLHCL= 50 pF 10% TC= +25C See figure 4 4.5 V 9 22 ns CL= 50 pF 10% TC= -55C and +125C See figure 4 4.5 V 10, 11 33 ns Transition time, high-to-low low-to-high tTHL, tTLH2

36、/ CL= 50 pF 10% TC= +25C See figure 4 4.5 V 9 15 ns CL= 50 pF 10% TC= -55C and +125C See figure 4 4.5 V 10, 11 22 ns 1/ For a power supply of 5 V 10 percent, the worst case output voltages (VOHand VOL) occur for HCT at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Wor

37、st cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. Power dissipation capacitance (CPD), is used to determine the dynamic power consumption, per gate, PD= VCC2fi(CPD+ CL) where: fi= input frequency, CL= output load capacitance, VCC= supply voltage 2/ Transition time (tTHL, tTLH), if not

38、tested, shall be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 AP

39、R 97 Device type 01 Case outline C Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCCFIGURE 1. Terminal connections. Device type 01 Truth table, each gate Inputs Output A B Y L L H H L H L H H H H L Positive logic Y = AB L = Low voltage level

40、 H = High voltage level FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Lo

41、gic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1 CL = 50 pF minimum or equivalent (inc

42、ludes probe and jig capacitance). 2 RL= 1 k or equivalent, RT= 50 or equivalent. 3 Input signal from pulse generator: VIN= 0.0 V to 3.0 V; tr 6.0 ns; tf 6.0 ns; duty cycle = 50 percent. 4 Timing parameters shall be tested at a minimum input frequency of 1MHz. 5 The outputs are measured one at a time

43、 with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86831 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHE

44、ET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality co

45、nformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring

46、 activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II h

47、erein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - -

48、 - Final electrical test parameters (method 5004) 1*, 2, 9 Group A test requirements (method 5005) 1, 2, 3, 4, 7, 9, 10, 11* Groups C and D end-point electrical parameters (method 5005) 1, 2, 3 * PDA applies to subgroup 1. * Subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table I. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall a

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