1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Delete vendor CAGE 27014. Change vendor CAGE 18714 to 34371. Editorial changes throughout. 90-11-26 M. A. Frye B Add notes to figure 4, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes thro
2、ughout. LTG05-11-10 Thomas M. Hess C Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-08-25 Thomas M. Hess REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY James E. Nicklaus DLA LAND AND MAR
3、ITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, BCD-TO-
4、7 SEGMENT LATCH/DECODER/DRIVER, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-03-03 REVISION LEVEL C SIZE A CAGE CODE 67268 5962-87733 SHEET 1 OF 13 DSCC FORM 2233 APR 97 5962-E465-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI
5、T DRAWING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 P
6、art or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87733 01 E A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number
7、 Circuit function 01 54HC4511 BCD-to-7 segment latch/decoder/driver 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 2 CQCC1-N20 20 Square chip carrier 1
8、.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode cur
9、rent 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 500 Mw 4/ Lead temperature (soldering, 10 seconds) 260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperatur
10、e (TJ) 175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +2.0 V dc to +6.0 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) 0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 2.0 V . 0 to 1000 ns VC
11、C= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ Th
12、e limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC
13、ROCIRCUIT DRAWING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time, A, B, C, or D to latch enable (ts): TC= +25C: VCC= 2.0 V . 100 ns VCC= 4.5 V . 20 ns VCC= 6.0 V . 1
14、7 ns TC= -55C to +125C: VCC= 2.0 V . 150 ns VCC= 4.5 V . 30 ns VCC= 6.0 V . 26 ns Minimum latch enable pulse width (tw): TC= +25C: VCC= 2.0 V . 80 ns VCC= 4.5 V . 16 ns VCC= 6.0 V . 14 ns TC= -55C to +125C: VCC= 2.0 V . 120 ns VCC= 4.5 V . 24 ns VCC= 6.0 V . 20 ns Minimum hold time, latch enable to
15、A, B, C, or D (th): TC= +25C: VCC= 2.0 V . 25 ns VCC= 4.5 V . 5 ns VCC= 6.0 V . 5 ns TC= -55C to +125C: VCC= 2.0 V . 40 ns VCC= 4.5 V . 8 ns VCC= 6.0 V . 7 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
16、part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STA
17、NDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are availabl
18、e online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5
19、962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the soli
20、citation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Assoc
21、iation, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulati
22、ons unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Ma
23、nufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-3853
24、5. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in acco
25、rdance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in a
26、ccordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circ
27、uit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 E
28、lectrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2
29、 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C”
30、shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate o
31、f compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product
32、 meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification
33、 of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentatio
34、n. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C
35、SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVIN= VIHor VILIOH= -20 A VCC= 2.0 V 1, 2, 3 All 1.9 V VCC= 4.5 V 4.4 VC
36、C= 6.0 V 5.9 VIN= VIHor VILIOH= -6.0 mA VCC= 4.5 V 3.7 VIN= VIHor VILIOH= -7.8 mA VCC= 6.0 V 5.2 Low level output voltage VOLVIN= VIHor VILIOL= +20 A VCC= 2.0 V 1, 2, 3 All 0.1 V VCC= 4.5 V 0.1 VCC= 6.0 V 0.1 VIN= VIHor VILIOL= +4.0 mA VCC= 4.5 V 0.4 VIN= VIHor VILIOL= +5.2 mA VCC= 6.0 V 0.4 High le
37、vel input voltage 2/ VIHVCC= 2.0 V 1, 2, 3 All 1.5 V VCC= 4.5 V 3.15 VCC= 6.0 V 4.2 Low level input voltage 2/ VILVCC= 2.0 V 1, 2, 3 All 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 Quiescent current ICCVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 All 160 A Input leakage current IINVCC= 6.0 V, VIN= VCCor GND 1, 2, 3 A
38、ll 1.0 A Input capacitance CINVCC= GND, TC= 25C See 4.3.1c 4 All 10.0 pF Functional tests See 4.3.1d 7, 8 All L H Propagation delay time, A, B, C, or D to output 3/ tPHL1, tPLH1CL= 50 pF See figure 4 VCC= 2.0 V 9 All 600 ns 10, 11 900 VCC= 4.5 V 9 120 10, 11 180 VCC= 6.0 V 9 102 10, 11 153 Propagati
39、on delay time, latch enable to output 3/ tPHL2, tPLH2CL= 50 pF See figure 4 VCC= 2.0 V 9 All 600 ns 10, 11 900 VCC= 4.5 V 9 120 10, 11 180 VCC= 6.0 V 9 102 10, 11 153 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN
40、DARD MICROCIRCUIT DRAWING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC+125C unless otherwise specified Group A subgroups Device type L
41、imits Unit Min Max Propagation delay time, blanking to output 3/ tPHL3, tPLH3CL= 50 pF See figure 4 VCC= 2.0 V 9 All 600 ns 10, 11 900 VCC= 4.5 V 9 120 10, 11 180 VCC= 6.0 V 9 102 10, 11 153 Propagation delay time, lamp test to output 3/ tPHL4, tPLH4CL= 50 pF See figure 4 VCC= 2.0 V 9 All 600 ns 10,
42、 11 900 VCC= 4.5 V 9 120 10, 11 180 VCC= 6.0 V 9 102 10, 11 153 Transition time 4/ tTLH, tTHLCL= 50 pF See figure 4 VCC= 2.0 V 9 All 75 ns 10, 11 110 VCC= 4.5 V 9 15 10, 11 22 VCC= 6.0 V 9 13 10, 11 19 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HC at 4.
43、5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IINand ICC) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
44、Power dissipation capacitance (CPD), typically 100 pF, determines the no load dynamic power consumption, PD= CPDVCC2f + ICCVCC, and the no load dynamic current consumption, IS= CPDVCCf + ICC. 2/ Tests are not required if applied as a forcing function for VOHand VOL. 3/ AC testing at VCC= 2.0 V and V
45、CC= 6.0 V shall be guaranteed, if not tested, to the specified limits in table I. 4/ Transition times( tTLH, tTHL), if not tested, shall be guaranteed to the specified limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
46、ING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type All Case outlines E 2 Terminal number Terminal symbol Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 B C LT BL LE D A GND e d c b a g f VCC- - - - NC B
47、 C LT BL NC LE D A GND NC e d c b NC a g f VCCNC = No internal connection. FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87733 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990
48、 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Inputs Outputs LE BL LT D C B A a b c d e f g Display X X L X X X X H H H H H H H 8 X L H X X X X L L L L L L L Blank L H H L L L L H H H H H H L 0 L H H L L L H L H H L L L L 1 L H H L L H L H H L H H L H 2 L H H L L H H H H H H L L H 3 L H H L H L L L H H L L H H 4 L H H L H L H H L H H L H H 5 L H H L H H L L L H H H H H 6 L H H L H H H H H H L L L L 7 L H H H L L L H H H H H H H 8 L H H H L L H H H H L L H H 9 L H H H L H L L L L L L L L Blank L H
