1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add test circuits in figure 3. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. - LTG 05-05-11 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 11-08-25 Thomas M. Hess
2、REV SHET REV SHET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY James E. Nicklaus DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AG
3、ENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY D. A. DiCenzo APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, ANALOG MULTIPLEXER/DEMULTIPLEXER, TRIPLE SINGLE POLE, DOUBLE-POSITION, MONOLITHIC SILICON DRAWING APPROVAL DATE 88-05-25 REVISION LEVEL B SIZE A CAGE CODE 67268 5
4、962-87754 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E477-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97
5、1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-87754 01 E A Drawing number De
6、vice type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54HC4053 Analog multiplexer/demultiplexer, triple single-pole, double-position 1.2.2 Case outline(s).
7、The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply
8、voltage range (VCC) -0.5 V dc to +7.0 V dc Supply voltage range (VCC-VEE) . -0.5 V dc to +11.0 V dc Supply voltage range (VEE) +0.5 V dc to -7.0 V dc DC input diode current (IIK): (VIVCC+ 0.5 V dc) 20 mA DC output diode current (IOK): (VIVCC+ 0.5 V dc) 20 mA DC switch current: (VI VEE 0.5 V dc or VI
9、 VCC+ 0.5 V dc) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) -65C to +150C Maximum power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) . +175C 1/ St
10、resses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall ap
11、ply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ For TC= +100C to +125C, derate linearly at 12 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARI
12、TIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) . +2.0 V dc to +6.0 V dc Supply voltage range (VEE) . 0.0 V dc to -6.0 V dc Supply voltage range (VCC-VEE) +2.0 V dc to +10.0 V dc DC input voltage, digital
13、inputs (VI) . 0.0 V dc to VCCDC input voltage, analog inputs (VIS) VEEto VCCCase operating temperature range (TC) -55C to +125C Input rise or fall time (tr, tf) : VCC= 2.0 V . 0 to 1000 ns VCC= 4.5 V . 0 to 500 ns VCC= 6.0 V . 0 to 400 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standar
14、ds, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrat
15、ed Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HD
16、BK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(
17、s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced
18、 High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the ref
19、erences cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38
20、535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed
21、 as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form,
22、fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. Provided by IHSNot for ResaleNo reproduction or networking permitted without
23、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38
24、535, appendix A and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Switching waveforms and test
25、circuits. The switching waveforms and test circuits shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range.
26、 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
27、in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicato
28、r “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certifi
29、cate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers p
30、roduct meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notifi
31、cation of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required docume
32、ntation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE
33、VEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC+125C VEE= 0 V dc unless otherwise specified Device type Group A subgroups Limits Unit Min Max High level input voltage VIHVCC= 2.0 V All 1, 2, 3 1.5 V VCC= 4.5 V 3.15 VCC= 6.0
34、V 4.2 Low level input voltage VILVCC= 2.0 V All 1, 2, 3 0.3 V VCC= 4.5 V 0.9 VCC= 6.0 V 1.2 “ON” resistance RONVIS= VEEor VCCVI= VIHor VILIS 1.0 mA VCC= 4.5 V VEE= 0.0 V All 1 160 2, 3 240 VCC= 4.5 V VEE= -4.5 V 1 1202, 3 180 Peak “ON” resistance RON(peak) VIS= VEEor VCCVI= VIHor VILIS 1.0 mA VCC= 4
35、.5 V VEE= 0.0 V All 1 200 2, 3 300 VCC= 4.5 V VEE= -4.5 V 1 1302, 3 195 Control input leakage current IINVI= VCCor GND VCC= 6.0 V All 1, 2, 3 1.0 A Switch “ON/OFF” leakage current (2 channels) IIZVI= VIHor VILVOS= VCCor VEEVIS= VCCor GND VCC= 6.0 V VEE= 0.0 V All 1, 2, 3 1.0 A VIS= VIHor VILVCC= 5.0
36、 V VEE= -5.0 V All 1, 2, 3 2.0 Quiescent supply current ICCVI= VCCor GND IO= 0.0 mA VCC= 6.0 V VEE= 0.0 V All 1, 2, 3 160 A VCC= 5.0 V VEE= -5.0 V 320 Input capacitance CINTC= +25C, see 4.3.1c All 4 10 pF Functional tests See 4.3.1d All 7 L H Propagation delay time, switch IN to OUT 2/ tPHL, tPLHCL=
37、 50 pF 10% See figure 3 VCC= 2.0 V All 9 60 ns 10, 11 90 VCC= 4.5 V 9 12 10, 11 18 VCC= 6.0 V 9 10 10, 11 15 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND M
38、ARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC+125C VEE= 0 V dc unless otherwise specified Device type Group A subgroups Limits Unit Min Max Propagation delay time, cha
39、nnel select to switch output (switch turn “OFF”) 2/ tPHZ, tPLZCL= 50 pF 10% See figure 3 VCC= 2.0 V All 9 210 ns 10, 11 315 VCC= 4.5 V 9 42 10, 11 63 VCC= 6.0 V 9 36 10, 11 54 Propagation delay time, channel select to switch output (switch turn “ON”) 2/ tPZL, tPZHCL= 50 pF 10% See figure 3 VCC= 2.0
40、V All 9 220 ns 10, 11 330 VCC= 4.5 V 9 44 10, 11 66 VCC= 6.0 V 9 37 10, 11 56 1/ For a power supply of 5.0 V 10%, the worst case “ON” resistance (RON) occur at VCC= 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst case VIHand VILoccur at VCC= 5.5 V and 4.5 V, respe
41、ctively. (The VIHvalue at 5.5 V is 3.85 V). The worst case leakage currents (IIN, ICC, and IIZ) occur for CMOS at the higher voltage so the 6.0 V value should be used. Power dissipation capacitance (CPD), typically 45 pF, determines the no-load dynamic power consumption (PD) and the no-load dynamic
42、current consumption (IS). Where PD= CPDVCC2f + ICCVCCIS= CPDVCCf + ICCf is the frequency of the input signal. 2/ AC testing at VCC= 2.0 V and VCC= 6.0 V shall be guaranteed, if not tested, to the specified parameters. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
43、se from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type All Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B1* B0* C1* Cn* C0* E VEEGND S2 S1 S0 A
44、0* A1* An* Bn* VCC* Channel IN/OUT. * Common OUT/IN. FIGURE 1. Terminal connections. Inputs Outputs Enable S0 S1 S2 “ON” channels L L L L A0, B0, C0 L L L H A0, B0, C1 L L H L A0, B1, C0 L L H H A0, B1, C1 L H L L A1, B0, C0 L H L H A1, B0, C1 L H H L A1, B1, C0 L H H H A1, B1, C1 H X X X None H = H
45、igh voltage level L = Low voltage level X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSC
46、C FORM 2234 APR 97 FIGURE 3. Switching waveforms and test circuits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-87754 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 223
47、4 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspecti
48、on. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C,
