1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 04-07-29 Raymond Monnin B Update drawing as part of 5 year review. -jt 12-01-18 C. SAFFLE THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. R
2、EV SHEET REV SHEET REV STATUS REV B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Thanh V. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGE
3、NCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, BIPOLAR, LOW POWER SCHOTTKY, TTL, 8-BIT SHIFT REGISTER WITH INPUT LATCHES, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-04-19 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89444
4、 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E131-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE
5、1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89444 01 E A Drawing number Device type
6、 (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 54LS597 8-bit shift register with input latches 1.2.2 Case outlines. The case outlines are as designated in MIL-ST
7、D-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 dual-in-line F GDFP2-F16 or CDFP3-F16 16 flat 2 CQCC1-N20 20 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum rati
8、ngs. Supply voltage range (VCC) . -0.5 V minimum dc to +7.0 V dc maximum Input voltage range (excluding I/O ports) -1.5 V dc at 18 mA to +7.0 V dc Off-state output voltage range (including I/O ports) -1.5 V dc at 18 mA to +5.5 V dc Storage temperature range -65C to +150C Maximum power dissipation (P
9、D) . 291.5 mW 1/ Lead temperature (soldering, 10 seconds) . +300C Junction temperature (TJ) +175C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V minimum dc to +5.5 V maximum dc Minimum high level input voltage (VIH
10、) . 2.0 V dc Maximum low level input voltage (VIL) 0.7 V dc Maximum input clamp current (IIK) . -18 mA Maximum high level output Current (IOH) -1.0 mA Maximum low level output current (IOL) 8.0 mA Case operating temperature range (TC) . -55C to +125C _ 1/ Maximum power dissipation is defined as VCC
11、X ICC, and must withstand the added PD due to short circuit test e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC
12、FORM 2234 APR 97 1.4 Recommended operating conditions - Continued. Minimum setup time (ts): Data before RCK 20 ns SRCLR inactive before SRCK . 25 ns SRLOAD inactive before SRCK 30 ns RCK before SRLOAD 2/ 40 ns SER before SRCK 20 ns Minimum hold time (th) . 0 ns Minimum pulse width (tw): SRCK high 15
13、 ns SRCK low . 35 ns RCK 20 ns SRCLR 20 ns SRLOAD . 40 ns Maximum shift clock frequency (fclock) 20 MHz 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Un
14、less otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits
15、. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or
16、from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, howe
17、ver, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 2/ The RCK before SRLOAD setup time ensures the data saved by RCK will also be loaded into the shift register. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH
18、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B
19、 devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the ma
20、nufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These mod
21、ifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as speci
22、fied in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic dia
23、gram. The logic diagram shall be as specified on figure 3. 3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics
24、 are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be
25、 in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not m
26、arking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-
27、38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritim
28、e -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
29、with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring a
30、ctivity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO
31、CIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Uni
32、t Min Max High level output voltage VOHVCC= 4.5 V, VIL= 0.7 V, VIH= 2.0 V, IOH= -1 mA 1, 2, 3 All 2.4 V Low level output voltage VOLVCC= 4.5 V, VIL= 0.7 V, VIH= 2.0 V, IOL= 8 mA 1, 2, 3 All 0.4 V Input clamp voltage VIKVCC= 4.5 V, IIN= -18 mA 1, 2, 3 All -1.5 V High level input current IIH1VCC= 5.5
33、V, VIN= 2.7 V 1, 2, 3 All 20 A IIH2VCC= 5.5 V, VIN= 7.0 V 1, 2, 3 All 0.1 mA Low level input current IILVCC= 5.5 V, SER, A thru H 1, 2, 3 All -0.4 mA VIN= 0.4 V Others 1, 2, 3 All -0.2 mA Short circuit output current IOSVCC= 5.5 V, VOUT= 0.0 V 1/ 1, 2, 3 All -20 -100 mA Supply current (total) ICCHVC
34、C= 5.5 V, All possible inputs grounded, All outputs open 1, 2, 3 All 53 mA ICCL1, 2, 3 All 53 mA Functional tests See 4.3.1c, VCC= 4.5 V, 5.5 V 7, 8 All Propagation delay time, tPLH1RL= 1 k 9 All 23 ns SRCK to QHCL= 30 pF 10, 11 All 32 tPHL1see figure 4 9 All 30 ns 10, 11 All 42 Propagation delay ti
35、me, tPLH29 All 57 ns SRLOAD to QH10, 11 All 80 tPHL29 All 44 ns 10, 11 All 62 Propagation delay time, tPHL39 All 36 ns SRCLR to QH10, 11 All 50 Propagation delay time, tPLH4SRLOAD = Low 9 All 60 ns RCK to QH10, 11 All 84 tPHL49 All 48 ns 10, 11 All 67 1/ Not more than one output will be shorted at o
36、ne time and the duration of the short circuit condition shall not exceed one second. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEE
37、T 6 DSCC FORM 2234 APR 97 Device type 01 Case outlines E and F 2 Terminal number Terminal symbol 1 B NC 2 C B 3 D C 4 E D 5 F E 6 G NC 7 H F 8 GND G 9 QHH 10 SRCLR GND 11 SRCK NC 12 RCK QH13 SRLOAD SRCLR 14 SER SRCK 15 A RCK 16 VCCNC 17 - - - SRLOAD 18 - - - SER 19 - - - A 20 - - - VCCNC = No connec
38、tion FIGURE 1. Terminal connections. RCK SRCK SRLOAD SRCLR Function X X X Data loaded to input latches X L H Data loaded from inputs to shift register no clock edge X L H Data transferred from input latches to shift register X X L L Invalid logic; state of shift register indeterminate when signals r
39、emoved X X H L Shift register cleared X H H Shift register clocked, Qn= Qn-1, Q0= SER H = High level voltage L = Low level voltage X = Irrelevant = Low-to-high clock transition FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST
40、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A
41、 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. RL= Load resistor; see table I for value. 2. CL= Load capacitance includes jig and probe capacitance; see table I for value. 3. All diodes ar 1N3064 or equivalent. 4. All input pulses
42、 have the following characteristics: PRR 1 MHz, ZOUT 50, tr 15 ns, tf 6 ns. 5. The outputs are measured one at a time with one input transition per measurement. FIGURE 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I
43、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89444 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening.
44、Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be mai
45、ntained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015
46、of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test re
47、quirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) - - - Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9 Group A test requirements (method 5005) 1, 2, 3, 7, 8, 9, 10*, 11* Groups C and D end-point electrical parame
48、ters (method 5005) 1, 2, 3 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 4, 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroups 7 and 8 shall include
