1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update to reflect latest changes in format and requirements. Editorial changes throughout. -les 05-03-01 Raymond Monnin B Update drawing as part of 5 year review. -jt 12-02-28 C. SAFFLE THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. R
2、EV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Tim H. Noh DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AN
3、D AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Raymond Monnin APPROVED BY Michael A. Frye MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, TRANSCEIVERS/REGISTERS, MONOLITHIC SILICON DRAWING APPROVAL DATE 89-05-05 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89558 SHEET 1 OF 12 DS
4、CC FORM 2233 APR 97 5962-E203-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This d
5、rawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89558 01 K X Drawing number Device type (see 1.2.1) Case
6、 outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type. The device type identify the circuit function as follows: Device type Generic number Circuit function 01 54F652 Octal transceiver/register with three-state output 1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835
7、and as follows: Outline letter Descriptive designator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat L GDIP3-T24 or CDIP4-T24 24 dual-in-line 3 CQCC1-N28 28 leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings.
8、Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range . -0.5 V dc to +7.0 V dc Input current range -30 mA to +5.0 mA Voltage applied to any output in the disabled state . -0.5 V dc to +5.5 V dc Voltage applied to any output in the high state -0.5 V dc to VCCCurrent into any output in the l
9、ow state . 96 mA Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1/ 825 mW Lead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage (VCC)
10、 . +4.5 V dc minimum to +5.5 V dc maximum Minimum high level input voltage (VIH) . 2.0 V dc Maximum low level input voltage (VIL) 0.8 V dc Case operating temperature range (TC) -55C to +125C _ 1/ Maximum power dissipation is defined as VCCx ICC, and must withstand the added PDdue to short-circuit te
11、st; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions - Conti
12、nued. Maximum clock frequency (fmax): VCC= 5.0 V, TC= +25C . 90 MHz VCC= 4.5 V, 5.5 V; TC= +125C, -55C 75 MHz Hold time An, Bn to CPAB, CPBA (th): VCC= 5.0 V, TC= +25C . 1.5 ns VCC= 4.5 V, 5.5 V; TC= +125C, -55C 2.5 ns Set up time An, Bn to CPAB, CPBA (ts) . 5 ns Pulse width, CPAB, CPBA (tw) . 5 ns
13、2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.
14、 DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS
15、MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-50
16、94.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIR
17、EMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacture
18、r or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM
19、) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the Q
20、ML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The
21、 terminal connections shall be as specified on figure 1. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3.
22、2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance charac
23、teristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking
24、 shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option
25、 of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with
26、 MIL-PRF-38535 to identify when the QML flow option is used 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and
27、 Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be p
28、rovided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acq
29、uiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDA
30、RD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max
31、High level output voltage VOHVCC= 4.5 V, IOH= -12 mA, 1, 2, 3 All 2.0 V VIL= 0.8 V, VIH= 2.0 V Low level output voltage VOLVCC= 4.5 V, IOL= 48 mA, VIL= 0.8 V, VIH= 2.0 V 1, 2, 3 All 0.55 V Input clamp voltage VI CVCC= 4.5 V, II N= -18 mA 1, 2, 3 All -1.2 V High level input current IIH1VCC= 5.5 V, VI
32、N= 2.7 V (non-I/O pins) 1, 2, 3 All 20 A 1/ IIH2VCC= 5.5 V, VIN= 7.0 V 100 IIH3VCC= 5.5 V, VIN= 5.5 V (I/O pins) 1.0 mA Low level input current 1/ IILVCC= 5.5 V, VIN= 0.5 V (non-I/O pins) 1, 2, 3 All -600 A Short circuit output current IOSVCC= 5.5 V, VOUT= 0.0 V 2/ 1, 2, 3 All -100 -225 mA Off state
33、 output current IOZHVCC= 5.5 V, VIN= 2.7 V 1, 2, 3 All 70 A IOZLVIH= 2.0 V VIN= 0.5 V -650 Supply current ICCHVCC= 5.5 V 1, 2, 3 All 135 mA ICCL150 ICCZ 150 Functional tests See 4.3.1c 3/ 7, 8 All See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted wit
34、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C unless otherwise specified Group
35、A subgroups Device type Limits Unit Min Max Propagation delay time, tPLH1CL= 50 pF, VCC= 5.0 V 9 All 1 7 ns from An, Bn to Bn, An R1= 500 , VCC = 4.5 V to 5.5 V 10, 11 1 8 tPHL1R2= 500 , VCC = 5.0 V 9 All 1 6.5 ns See figure 3 VCC= 4.5 V to 5.5 V 10, 11 1 8 Propagation delay time, tPLH2VCC= 5.0 V 9
36、All 2 7 ns from CPBA, CPAB to VCC= 4.5 V to 5.5 V 10, 11 2 8.5 An, Bn tPHL2VCC= 5.0 V 9 All 2 8 ns VCC= 4.5 V to 5.5 V 10, 11 2 9.5 Propagation delay time, tPLH3VCC= 5.0 V 9 All 2 8.5 ns from SBA, SAB to An, Bn VCC= 4.5 V to 5.5 V 10, 11 2 11 tPHL3VCC= 5.0 V 9 All 2 8 ns VCC= 4.5 V to 5.5 V 10, 11 2
37、 10 Output enable time, tPZH1VCC= 5.0 V 9 All 2 8.5 ns from OEBA to An VCC= 4.5 V to 5.5 V 10, 11 2 10 tPZL1VCC= 5.0 V 9 All 2 8.5 ns VCC= 4.5 V to 5.5 V 10, 11 2 10 Output enable time, tPZH2VCC= 5.0 V 9 All 2 8.5 ns from OEBA to Bn VCC= 4.5 V to 5.5 V 10, 11 2 10 tPZL2VCC= 5.0 V 9 All 2 10 ns VCC=
38、4.5 V to 5.5 V 10, 11 2 12 Output disable time, tPHZ1VCC= 5.0 V 9 All 1 7.5 ns from OEBA to An VCC= 4.5 V to 5.5 V 10, 11 1 9 tPLZ1 VCC= 5.0 V 9 All 1 7.5 ns VCC= 4.5 V to 5.5 V 10, 11 1 9 Output disable time, tPHZ2VCC= 5.0 V 9 All 1 7.5 ns from OEBA to Bn VCC= 4.5 V to 5.5 V 10, 11 1 9 tPLZ2 VCC= 5
39、.0 V 9 All 1 10 ns VCC= 4.5 V to 5.5 V 10, 11 1 12 1/ For I/O ports the parameters IIHand IILinclude the off-state output current. 2/ Not more than one output will be shorted at one time and the duration of the test condition shall not exceed 1 second. 3/ Functional tests shall be conducted at input
40、 test conditions of GND VIL VOLand VOH VIH VCC. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 Device type
41、 01 Case outlines K and L 3 Terminal number Terminal symbol Terminal symbol 1 CPAB NC 2 SAB CPAB 3 OEAB SAB 4 A1 OEAB 5 A2 A1 6 A3 A2 7 A4 A3 8 A5 NC 9 A6 A4 10 A7 A5 11 A8 A6 12 GND A7 13 B8 A8 14 B7 GND 15 B6 NC 16 B5 B8 17 B4 B7 18 B3 B6 19 B2 B5 20 B1 B4 21 OEBA B3 22 SBA NC 23 CPBA B2 24 VCCB1
42、25 - - - OEBA 26 - - - SBA 27 - - - CPBA 28 - - - VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEE
43、T 8 DSCC FORM 2234 APR 97 Inputs Inputs/outputs 1/ Operating OEBA OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7 mode L H H/L H/L X X Input Input Isolation L H X X Input Input Store A and B data X H H/L X X Input Not specified Store A, hold B H H X X Input Output Store A in both registers L X H/L X X
44、Not specified Input Hold A, store B L L X X Output Input Store B in both registers L L X X X L Output Input Real time B data to A bus L L X H/L X H Output Input Store B data to A bus H H X X L X Input Output Real time A data to B bus H H H/L X H X Input Output Stored A data to B bus H L H/L H/L H H
45、Output Output Stored A data to B bus and stored B data to A bus H = High voltage level L = Low voltage level X = Irrelevant = Low to high clock transition H/L = High or low voltage level 1/ The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input fun
46、ctions are always enabled, i.e., data at the bus pins will be stored on every low to high transition on the clock inputs. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND
47、AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 FIGURE 3. Test circuit and switching waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89558 DLA LAND AND MARITIM
48、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses have the follow
