1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated drawing to reflect MIL-H-38534 processing. Editorial changes throughout. 91-05-29 W. Heckman B Added case outlines X and Y. Editorial changes throughout. 93-08-31 K. A. Cottongim C Changes in accordance with NOR 5962-R037-94 93-11-12 K. A
2、. Cottongim D Added class K device as device type 02. Redrew entire document. -sld 98-04-10 K. A. Cottongim E Updated drawing to reflect the current requirements of MIL-PRF-38534. -sld 03-05-15 Raymond Monnin F Update drawing. -gz 09-04-21 Joseph D. RodenbeckTHE ORIGINAL FIRST SHEET OF THIS DRAWING
3、HAS BEEN REPLACED. REV SHEET REV F SHEET 15 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Steve Duncan DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Donald R. Osborne COLUMBUS, OHIO 43218-3990 http:/www.dscc
4、.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY William K. Heckman MICROCIRCUIT, HYBRID, LINEAR, DUAL CHANNEL, LINE RECEIVER, OPTOCOUPLER AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-08-17 AMSC N/A REVISION LEVEL F SIZE A CAGE CODE 67268 5962-89572 SHE
5、ET 1 OF 15 DSCC FORM 2233 APR 97 5962-E286-09Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SC
6、OPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance le
7、vels are reflected in the PIN. For class H devices: 5962-89572 01 E X Drawing number Device type Case outline Lead finish (see 1.2.2) (see 1.2.4) (see 1.2.5) For class K devices: 5962 - 89572 02 K E X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (se
8、e 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA dev
9、ice. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 HCPL-1931 Dual channel line receiver optocoupler 02 HCPL-193K Dual channel line receiver optocoupler 1.2.3 Device class designator. This device class designator shal
10、l be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device perfor
11、mance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard mi
12、litary quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). Provided by IHSNot f
13、or ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 3 DSCC FORM 2234 APR 97 E Designates devices which are based upon one of the other classes (K,
14、 H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer speci
15、fied quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package styl
16、e E CDIP2-T16 16 Dual-in-line X See figure 1 16 Dual-in-line Y See figure 1 16 Dual-in-line 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC), 1 minute maximum . +7.0 V dc Enable input voltage, per channel (VEE) . +
17、5.5 V dc Output collector voltage, per channel (VO) . +7.0 V dc Forward input current, per channel (IF) 2/. 60 mA Reverse input current (IR) . 60 mA Output collector current, per channel (IO) . 25 mA Storage temperature range. -65C to +150C Lead temperature (soldering, 10 seconds). +260C Output coll
18、ector power dissipation, per channel. 40 mW Total input power dissipation, per channel . 168 mW Total package power dissipation (PD). 564 mW Thermal resistance, junction-to-case (JC): Case outline E. See MIL-STD-1835 Case outlines X and Y. 28C/W Case temperature +170C 1.4 Recommended operating condi
19、tions. Positive supply voltage range (VCC) +4.5 V dc to +5.5 V dc Low level enable voltage range (VEL) 0 V dc to +0.8 V dc High level enable voltage range (VEH) +2.0 V dc to VCCLow level input current range (IIL) . 0 A to 250 A High level input current range (IIH) 3/ 12.5 mA to 60 mA Maximum fan-out
20、 (TTL load) (N). 5 Ambient operating temperature range (TA). -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derate linearly at 1.2 mA/C above TA= +100C.
21、3/ 12.5 mA condition permits at least 20 percent current transfer ratio degradation guardband. Initial switching threshold is 10 mA or less. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DEFENSE SUPPL
22、Y CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwis
23、e specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface
24、Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ from the Standardization Do
25、cument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable
26、laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tes
27、ts herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for
28、 the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-
29、38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Logic diagram(
30、s). The logic diagram(s) shall be as specified on figure 4. 3.2.5 Test circuit for propagation delays. The test circuit for propagation delays shall be as specified on figure 5. 3.2.6 Test circuit and waveforms for common mode transient immunity. The test circuit and waveforms for common mode transi
31、ent immunity shall be as specified on figure 6. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 5 DSCC FORM 2234 APR 97 3.
32、3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the sub
33、groups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may a
34、lso be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed he
35、rein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.7 Certificat
36、e of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Ce
37、rtificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in
38、the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DE
39、FENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Min Max Unit High level ou
40、tput current, per channel IOHVCC= 5.5 V, VO= 5.5 V, II= 250 A, VE= 2.0 V 1, 2, 3 All 250 Low level output voltage, per channel VOLVCC= 5.5 V, IO= 10 mA, VF= 2.0 V, IOL(sinking) = 10 mA 1, 2, 3 All 0.6 V II= 10 mA 2.60 Input voltage , per channel VIII= 60 mA 1, 2, 3 All 2.75 V Input reverse voltage,
41、per channel VRIR= 10 mA 1, 2, 3 All 1.10 V Low level enable current, per channel IELVCC= 5.5 V, VE= 0.5 V 1, 2, 3 All -2.0 mA High level enable voltage, per channel VEH1/ 1, 2, 3 All 2.0 V Low level enable voltage, per channel VEL1, 2, 3 All 0.8 V High level supply current, both channels ICCHVCC= 5.
42、5 V, II= 0, VE= 0.5 V 1, 2, 3 All 28 mA Low level supply current, both channels ICCLVCC= 5.5 V, II= 60 mA, VE= 0.5 V 1, 2, 3 All 36 mA Input-output insulation 2/ leakage current II-ORelative humidity = 45%, t = 5.0 s, VI-O= 1500 V dc 1 All 1.0 A 9 100 ns Propagation delay time to high output level,
43、per channel tPLHCL = 50 pF, RL= 510, II= 13 mA, see figure 5 3/ 4/ 10, 11 All 140 ns 9 100 ns Propagation delay time to low output level, per channel tPHLCL = 50 pF, RL= 510, II= 13 mA, see figure 5 4/ 5/ 10, 11 All 120 ns Common mode transient immunity at high output level, per channel 8/ CMH VCM=
44、50 V (peak), II= 0 mA, VO= (min) = 2.0 V, RL= 510, see figure 6 4/ 6/ 9, 10, 11 All 1000 V/s Common mode transient immunity at low output level, per channel 8/ CML VCM= 50 V (peak), II= 10 mA, VO= (max) = 0.8 V, RL= 510, see figure 6 4/ 7/ 9, 10, 11 All 1000 V/s See footnotes at top of next page. Pr
45、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89572 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL F SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Co
46、ntinued. 1/ No external pull up is required for a high logic state on the enable input. 2/ The device is considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together. 3/ The tPLHpropagation delay is measured from the 6.5 mA point on the trailing
47、 edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 4/ In addition to the electrical test requirements of table I, subgroups 9, 10, and 11 testing shall be sufficient to verify the truth table on figure 3. 5/ The tPHLpropagation delay is measured from the 6.5 mA poi
48、nt on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. 6/ CMHis the maximum tolerable rate of rise of the common voltage to assure that the output will remain in a high logic state (i. e., VOUT 2.0 V). 7/ CMLis the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT 0.8 V).
