DLA SMD-5962-90502 REV A-2010 MICROCIRCUIT DIGITAL BIPOLAR ADVANCED SCHOTTKY TTL 8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements . Editorial changes throughout. - gap 10-02-18 Charles F. Saffle The original first sheet of this drawing has been replaced. REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5

2、 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Larry T. Gauder DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Tim H. Noh APPROVED BY Willia

3、m K. Heckman MICROCIRCUIT, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY, TTL, 8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 90-02-05 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90502 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E488-09 Provided by IHSNot for Res

4、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-8

5、83 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-90502 01 K X Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 De

6、vice type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54F198 8-bit bidirectional universal shift register 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive design

7、ator Terminals Package style K GDFP2-F24 or CDFP3-F24 24 flat package L GDIP3-T24 or CDIP4-T24 24 dual-in-line package 3 CQCC1-N28 28 square chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range -0.5 V dc to +

8、7.0 V dc Input voltage range . -0.5 V dc to +7.0 V dc Input current range -30 mA to +5 mA Voltage applied to output in high output state range . -0.5 V to +VCCCurrent applied to output in low output state . +40 mA Storage temperature range . -65C to +150C Maximum power dissipation (PD) 1/ . 610 mW L

9、ead temperature (soldering, 10 seconds) . +300C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Junction temperature (TJ) . +175C _ 1/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

10、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Minimum high level input voltage (VIH)

11、2.0 V dc Maximum low level input voltage (VIL) . 0.8 V dc Input clamp current (IIK) . -18 mA High level output current (IOH) . -1 mA Low level output current (IOL) 20 mA Case operating temperature range (TC) -55C to +125C Minimum setup time, Dn to CP, (tS(H): TC= +25C 0.0 ns TC= -55C, +125C . 1.0 ns

12、 Minimum setup time, Dn to CP, (tS(L): TC= +25C 3.0 ns TC= -55C, +125C . 3.5 ns Minimum hold time, Dn to CP, (th(H): TC= +25C 0.0 ns TC= -55C, +125C . 2.5 ns Minimum hold time, Dn to CP, (th(L): TC= +25C 3.5 ns TC= -55C, +125C . 5.0 ns Minimum setup time, DSR, DSL, to CP, (tS(H): TC= +25C 0.0 ns TC=

13、 -55C, +125C . 1.5 ns Minimum setup time, DSR, DSL, to CP, (tS(L): TC= +25C 3.0 ns TC= -55C, +125C . 3.5 ns Minimum hold time, DSR, DSL, to CP, (th(H): TC= +25C 0.0 ns TC= -55C, +125C . 1.5 ns Minimum hold time, DSR, DSL, to CP, (th(L): TC= +25C 2.5 ns TC= -55C, +125C . 3.5 ns Minimum setup time, Sn

14、 to CP, (tS(H): TC= +25C 9.0 ns TC= -55C, +125C . 11.0 ns Minimum setup time, Sn to CP, (tS(L): TC= +25C 6.0 ns TC= -55C, +125C . 7.5 ns Minimum hold time, Sn to CP, (th(H), th(L): TC= +25C 0.0 ns TC= -55C, +125C . 0.0 ns Minimum CP pulse width, (tW(H), tW(L): TC= +25C 5.0 ns TC= -55C, +125C . 6.0 n

15、s Minimum MR$ $ $ $ $pulse width, (tW(L): TC= +25C 5.0 ns TC= -55C, +125C . 6.0 ns Minimum recovery time MR$ $ $ $ $to CP, (trec): TC= +25C 5.0 ns TC= -55C, +125C . 6.5 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

16、SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent sp

17、ecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Stan

18、dard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mi

19、l/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in t

20、his document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Pr

21、oduct built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan an

22、d qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN

23、as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A an

24、d herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as

25、specified on figure 3. 3.2.5 Test circuit and switching waveforms. Test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall a

26、pply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted

27、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN liste

28、d in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indica

29、tor “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certi

30、ficate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the

31、 requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change

32、 to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at t

33、he option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality co

34、nformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring

35、 activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II h

36、erein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUM

37、BUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min Max High level output voltage VOHVCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V, IOH= -1 mA 1, 2,

38、 3 2.5 V Low level output voltage VOLVCC= 4.5 V, VIL= 0.8 V, VIH= 2.0 V, IOL= 20 mA 1, 2, 3 0.50 V Input clamp voltage VIKVCC= 4.5 V, II= -18 mA 1, 2, 3 -1.2 V High level input current IIH1VCC= 5.5 V, VI= 2.7 V 1, 2, 3 20 A Input clamp current at maximum input voltage IIH2 VCC= 5.5 V, VI= 7.0 V 1, 2

39、, 3 100 A Low level input current IILVCC= 5.5 V, VI= 0.5 V 1, 2, 3 -0.6 mA Short circuit output current IOSVCC= 5.5 V 1/ 1, 2, 3 -60 -150 mA Supply current ICCHVCC= 5.5 V 1, 2, 3 100 mA ICCL110 Functional test See 4.3.1c 7, 8 Maximum clock frequency fMAXRL= 500 CL= 50 pF VCC= 5.0 V 9 80 MHz See figu

40、re 4 VCC= 4.5 V to 5.5 V 2/ 10, 11 70 Propagation delay time, CP to Qn tPLH1RL= 500 CL= 50 pF See figure 4 VCC= 5.0 V 9 5.0 10.0 ns VCC= 4.5 V to 5.5 V 10, 11 4.5 12.0 tPHL1VCC= 5.0 V 9 6.0 11.0 ns VCC= 4.5 V to 5.5 V 10, 11 5.5 13.0 Propagation delay time, MR$ $ $ $ $to Qn tPHL2VCC= 5.0 V 9 5.0 10.

41、0 ns VCC= 4.5 V to 5.5 V 10, 11 4.5 13.0 1/ Not more than one output should be shorted at a time, and the duration of the short circuit condition should not exceed 1 second. 2/ Guaranteed, if not tested, to the limts specified in table I. Provided by IHSNot for ResaleNo reproduction or networking pe

42、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outlines L and K 3 Terminal number Terminal symbols 1 S0 NC 2 DSRS0 3 D0 DSR4 Q0 D05 D1 Q0

43、6 Q1 D1 7 D2 Q1 8 Q2 NC 9 D3 D210 Q3 Q2 11 CP D3 12 GND Q3 13 MR$ $ $ $ $CP 14 Q4 GND 15 D4 NC 16 Q5 MR$ $ $ $ $17 D5 Q4 18 Q6 D4 19 D6 Q5 20 Q7 D5 21 D7 Q6 22 DSLNC 23 S1 D624 VCCQ7 25 D7 26 DSL27 S1 28 VCCFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking pe

44、rmitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Inputs Outputs MR$ $ $ $ $Mode CP Serial Parallel Q0 Q1 . . . Q6 Q7 S0 S1 Left Right D0 . . . D7 L X X X X X X

45、L L L L H X X L X X X Q00 Q10 Q60 Q70 H H H X X 0 . . . 7 0 1 6 7 H H L X H X H Q0n Q5n Q6n H H L X L X L Q0n Q5n Q6n H L H H X X Q1n Q2n Q7n H H L H L X X Q1n Q2n Q7n L H L L X X X X Q00 Q10 Q60 Q70 H = High voltage level L = Low voltage level X = Irrelevent = Low-to-high transition of designated i

46、nput. D0 . . . D7 = The level of steady-state input at inputs D0 through D7, respectively. Q00, Q10, Q60, Q70 = The level of Q0, Q1, Q6, Q7, respectively before the indicated steady-state input conditions were established. Q0n, Q1n, Q6n, Q7n = The level of Q0, Q1, Q6, Q7, respectively before the mos

47、t recent low-to-high clock transition. FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 9 DSCC FORM

48、2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90502 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 NOTES: 1. CLincludes probe and jig capacitance. 2. RT= Termination resistance should be equal to ZOUTof p

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