1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update, part of 5 year review. ksr 06-12-05 Raymond Monnin THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV SHET REV STATUS REV A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 PMIC N/A PREPARED BY Gary
2、 L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-09-11 M
3、ICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4K X 8 UVEPROM, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-90658 SHEET 1 OF 10 DSCC FORM 2233 APR 97 5962-E013-07 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT
4、 DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix
5、A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-90658 01 J A Drawing number Device type (see 1.2.1) Case outline(see 1.2.2) Lead finish(see 1.2.3)1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generi
6、c number Circuit function Acess time 01 57C43C-70 4K x 8-bit UVEPROM 70 ns 02 57C43C-55 4K x 8-bit UVEPROM 55 ns 03 57C43C-45 4K x 8-bit UVEPROM 45 ns 04 57C43C-35 4K x 8-bit UVEPROM 35 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Des
7、criptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line 1/ K GDFP2-F24 or CDFP3-F24 24 Flat pack 1/ L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1/ 3 CQCC1-N28 28 Square leadless chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
8、 1.3 Absolute maximum ratings. Voltage range on any pin with respect to ground.-0.6 V dc to +7.0 V dc Vpprange with respect to ground .-0.6 V dc to +14.0 V dc Storage temperature range-65C to +150C Maximum power dissipation (PD) 1 W Lead temperature (soldering, 10 seconds) +300C Thermal resistance,
9、junction-to-case (JC).See MIL-STD-1835 Junction temperature (TJ) 2/ +150C Temperature (under bias) range-55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC)+4.5 V dc to +5.5 V dc Ground voltage (GND).0 V dc Input high voltage (VIH) 2.0 V dc minimum Input low voltage (VIL)0.
10、8 V dc maximum Case operating temperature range (TC).-55C to +125C 1/ Lid shall be transparent to permit ultraviolet light erasure. 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Pr
11、ovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification
12、, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 -
13、 Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawing
14、s. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of preced
15、ence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirem
16、ents. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who
17、has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifica
18、tions to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used.
19、3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections sh
20、all be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in groups A, B, C, or D (see
21、4.3), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall
22、be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements.
23、 The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE S
24、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C 4.5V VCC 5.5V unless otherwise specified Group A subgroups Device types Min Max Units Input load current ILIVIN=
25、 5.5 V and GND 1,2,3 All -10 10 A Input leakage current IIXVIN= VCCand GND 1,2,3 All -10 10 A Output leakage current IOZVOUT= 5.5 V and GND 1,2,3 All -10 10 A VCCactive current (CMOS) ICC1CMOS inputs: 0 0.3 V or Vcc0.3 V 1/ 1,2,3 All 35 mA VCCactive current (TTL) ICC2TTL inputs: VIL 0.8 V, VIH 2.0 V
26、 1/ 1,2,3 All 50 mA Input high level voltage VIH1,2,3 All 2.0 VCC+0.3 V Input low level voltage VIL1,2,3 All -0.1 0.8 V Ouput high voltage VOHIOH= -4 mA 1,2,3 All 2.4 V Output low voltage VOLIOL= 16 mA 1,2,3 All 0.4 V Functional tests See 4.3.1d 7,8A,8B All Input capacitance CINVIN= 0 V 2/ 4 All 6 p
27、F Output capacitance COUTVOUT= 0 V 2/ TA= +25C f = 1 MHz 4 All 12 pF 01 70 02 55 03 45 Address to output delay tACCSee figure 3 9,10,11 04 35 ns 01-03 25 CS1/VPPto output delay tCS9,10,11 04 20 ns Output disable to output float tDFSee figure 3 3/ 9,10,11 All 25 ns Address to output hold tOHSee figur
28、e 3 9,10,11 All 0 ns 1/ Add 3 mA/MHz for ac power component. 2/ Tested initially and after any design or process changes that affect this parameter, and therefore shall be guaranteed to the limits specified in table I. 3/ May not be tested, but shall be guaranteed to the limits specified in table I.
29、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 Device types All Case outlines J, K, and L 3 Term
30、inal number Terminal symbol 1 A7NC 2 A6A73 A5A64 A4A55 A3A46 A2A37 A1A28 A0A19 O0A010 O1NC 11 O2O012 GND O113 O3O214 O4GND 15 O5NC 16 O6O317 O7O418 CS2 O519 A11O620 1CS /VPPO721 A10NC 22 A9CS2 23 A8A1124 VCC1CS /VPP25 - A1026 - A927 - A828 - VCCFIGURE 1. Terminal connections. Provided by IHSNot for
31、ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 Mode VCC1CS /VPPCS2 O0-O7Read 5.0 V 10% VILVIHDOUTOutput disable 5.0 V 10
32、% VIHX 1/ High Z Output disable 5.0 V 10% X 1/ VILHigh Z Program VCCVPPX 1/ DINProgram verify VCCVILVIHDOUT1/ X can be VILor VIH. FIGURE 2. Truth table. Test conditions (AC) Input pulse levels: GND to 3.0 V Input rise and fall times: 5 ns Input timing reference levels: 1.5 V Output reference levels:
33、 1.5 V FIGURE 3. AC read timing diagram and Test load circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM
34、 2234 APR 97 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations
35、, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ cert
36、ification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPROMS. When specified, devices shall be er
37、ased in accordance with the procedures and characteristics specified in 4.4 herein. 3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 herein. 3.6.3 Verification of erasure of programmed EPRO
38、MS. When specified, devices shall be verified as either programmed to specified program or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall const
39、itute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior
40、 to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each l
41、ot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.10 Verification and review. DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility
42、and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.11 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors. This reprogrammability test shall be done only for initial characteriz
43、ation and after any design or process changes which may affect reprogrammability of the device. This test shall consist of 25 program/erase cycles on 25 devices with the following conditions: a. All devices selected for testing shall be programmed in accordance with 3.2.3.2 herein. b. Verify pattern
44、 (see 3.6.3). c. Erase (see 3.6.1). d. Verify pattern erasure (see 3.6.3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90658 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
45、 8 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conf
46、ormance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing activity upon request. The
47、 test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim elect
48、rical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps: Margin test method. 3/ (1) At +25C, program greater than 95 percent of the bit locations, including the slowest programming cell. The remaining bits shall provide a worst case speed pattern. (2) Bake, unbiased, for 72 hours at +140C or for 32 hours at +150C or for 8 hours at +200C. (3) At +25C, perform a margin test using Vm= +5.8 V
