DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

上传人:brainfellow396 文档编号:699828 上传时间:2019-01-01 格式:PDF 页数:12 大小:192.19KB
下载 相关 举报
DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf_第1页
第1页 / 共12页
DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf_第2页
第2页 / 共12页
DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf_第3页
第3页 / 共12页
DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf_第4页
第4页 / 共12页
DLA SMD-5962-90703 REV B-2012 MICROCIRCUIT DIGITAL HIGH SPEED CMOS QUAD 2-INPUT INVERTING MULTIPLEXER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf_第5页
第5页 / 共12页
点击查看更多>>
资源描述

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add notes to figure 4, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 06-02-15 Thomas M. Hess B Correct output current condition for VOHand VOLtests in table I. Update boi

2、lerplate to MIL-PRF-38535 requirements. Editorial changes throughout. jak 12-02-23 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landand

3、maritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas J. Riccuiti THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, QUAD 2-INPUT INVERTING MULTIPLEXER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON AND AGENCIES OF THE DEPA

4、RTMENT OF DEFENSE DRAWING APPROVAL DATE 91-04-24 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90703 SHEET 1 OF 11 DSCC FORM 2233 APR 97 5962-E185-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90

5、703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines a

6、nd lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90703 01 M E A Federal stock class designator RHA des

7、ignator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desi

8、gnator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number C

9、ircuit function 01 54HCT158 Quad 2-input multiplexer, inverting, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the r

10、equirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive desi

11、gnator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

12、 from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC o

13、utput voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD) 2/ . 500 mW Lead temperature (soldering, 10 seconds) +300C Therma

14、l resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT) 0.0 V dc to VCCCase operating temperature range (TC)

15、. -55C to +125C Input rise or fall time (tr, tf): VCC= 4.5 V, 5.5 V 0 to 500 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified

16、, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interfa

17、ce Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization

18、 Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation o

19、r contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD-7-A - Standard for Description of 54/74HCXXXX and 54/74HCTXXXX High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, S

20、uite 240S, Arlington, VA 22201.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption

21、has been obtained. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ For TC= +100C to +125C, derate linearly at 12 mW/C. 3/ Unless otherwise specified, all voltages are r

22、eferenced to ground. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements.

23、 The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The

24、 individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-3853

25、5 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The trut

26、h table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation

27、parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be

28、 the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible

29、 due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accor

30、dance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compli

31、ance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed

32、as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of

33、 MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with ea

34、ch lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 V

35、erification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the

36、option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 39 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

37、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Group A subgroups Device type Limits U

38、nit Min Max High level output voltage VOHVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 1, 2, 3 All 4.4 V IOH= -4.0 mA 3.7 Low level output voltage VOLVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOL= +20 A 1, 2, 3 All 0.1 V IOL= +4.0 mA 0.4 High level input voltage VIHVCC= 4.5 V 2/ 1, 2, 3 All 2.0

39、 V Low level input voltage VILVCC= 4.5 V 2/ 1, 2, 3 All 0.8 V Quiescent supply current ICCVCC= 5.5 V, VIN= VCCor GND IOUT= 0.0 A 1, 2, 3 All 160 A Input leakage current IINVCC= 5.5 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Additional quiescent supply current, TTL inputs ICCAny one input VIN= 2.4 V or 0.5

40、V Other inputs VIN= VCCor GND VCC= 5.5 V 1, 2, 3 All 3.0 mA Input capacitance CINVIN= 0 V, see 4.4.1c 4 All 10 pF Power dissipation capacitance CPD3/ See 4.4.1c 4 All 44 pF Functional tests See 4.4.1b 7, 8 All Propagation delay time, mIn to mYtPHL1, tPLH1VCC= 4.5 V CL= 50 pF See figure 4 9 All 32 ns

41、 10, 11 48 Propagation delay time, Eto mYtPHL2, tPLH29 All 37 ns 10, 11 56 Propagation delay time, S to mYtPHL3, tPLH3 9 All 35 ns 10, 11 53 Transition time tTHL, tTLH4/ 9 All 15 ns 10, 11 22 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at VCC= 4.5 V.

42、 Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ Test is guaranteed if applied as a forcing function for VOHor VOLtests. 3/ Power dissipation capacitance (CPD) determines the dynamic power consumption (PD) a

43、nd the dynamic current consumption (IS): PD(total) = (CPD+ CL) VCC2f + (VCCx ICC) + (n x d x ICCx VCC) IS= (CPD+ CL) VCC f + ICC+ (n x d x ICC) f is input switching frequency; n is number of inputs switching; d is duty cycle; CLis load capacitance on each output. 4/ This parameter, if not tested, sh

44、all be guaranteed to the limits specified in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 Devic

45、e type All Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S 1I0 1I1 1Y2I0 2I1 2YGND 3Y3I1 3I0 4Y4I1 4I0 EVCCFIGURE 1. Terminal connections. Enable input Select input Data inputs Outputs ES mI0 mI1 mYH X X X H L L L X H L L H X L L H X L H L H X H L H = High vol

46、tage level L = Low voltage level X = Irrelevant FIGURE 2. Truth table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM

47、2234 APR 97 FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90703 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 NOTES: 1. CL = 50 pF (

48、includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN= 0.0 V to 3.0 V; PRR 1 MHz; ZO= 50; tr= 6.0 ns; tf= 6.0 ns; trand tfshall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 4. Switching waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted without license fro

展开阅读全文
相关资源
猜你喜欢
相关搜索

当前位置:首页 > 标准规范 > 国际标准 > 其他

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1