1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add notes to figure 5, switching waveforms and test circuit. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 06-02-23 Thomas M. Hess B Update test condition of high and low level output voltage (VOHand VOL) to
2、table I. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 12-07-25 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO
3、 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas J. Riccuiti APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, PRESETTABLE SYNCHRONOU
4、S 4-BIT BINARY UP/DOWN COUNTER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 91-11-26 REVISION LEVEL B SIZE A CAGE CODE 67268 5962-90848 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E420-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
5、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90848 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space applicatio
6、n (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90848
7、01 M E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA leve
8、ls and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit fu
9、nction as follows: Device type Generic number Circuit function 01 54HCT193 Presettable synchronous 4-bit binary up/down counter, asynchronous reset, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows:
10、 Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(
11、s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M.
12、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90848 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range
13、 (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+ 0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Clamp diode current 20 mA DC output current (per pin) 25 mA DC VCCor GND current (per pin) . 50 mA Storage temperature range (TSTG) . -65C to +150C Maximu
14、m power dissipation (PD) . 500 mW 4/ Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc
15、to VCCOutput voltage range (VOUT) 0.0 V dc to VCCCase operating temperature range (TC) . -55C to +125C Input rise or fall time (tr, tf): VCC= 4.5 V, 5.5 V 0 to 500 ns Minimum setup time, Pn to PL (ts): TC= +25C, VCC= 4.5 V . 15ns TC= -55C to +125C, VCC= 4.5 V . 22 ns Minimum CPU, CPD pulse width (tw
16、1): TC= +25C, VCC= 4.5 V . 23 ns TC= -55C to +125C, VCC= 4.5 V . 35 ns Minimum PL pulse width (tw2): TC= +25C, VCC= 4.5 V . 16 ns TC= -55C to +125C, VCC= 4.5 V . 24 ns Minimum MR pulse width (tw3): TC= +25C, VCC= 4.5 V . 20 ns TC= -55C to +125C, VCC= 4.5 V . 30 ns Minimum hold time, Pn to PL (th1):
17、TC= +25C, VCC= 4.5 V . 0 ns TC= -55C to +125C, VCC= 4.5 V . 0 ns Minimum hold time, CPD to CPU, CPU to CPD (th2): TC= +25C, VCC= 4.5 V . 16 ns TC= -55C to +125C, VCC= 4.5 V . 24 ns Minimum recovery time, PL to CPU, PL to CPD (tREC1): TC= +25C, VCC= 4.5 V . 15 ns TC= -55C to +125C, VCC= 4.5 V . 22 ns
18、 Minimum recovery time, MR to CPU, MR to CPD (tREC2): TC= +25C, VCC= 4.5 V . 5 ns TC= -55C to +125C, VCC= 4.5 V . 5 ns Maximum CPU, CPD frequency (fMAX): TC= +25C, VCC= 4.5 V . 22 MHz TC= -55C to +125C, VCC= 4.5 V . 15 MHz _ 1/ Stresses above the absolute maximum rating may cause permanent damage to
19、 the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55
20、C to +125C. 4/ For TC= +100C to +125C, derate linearly at 8 mW/C to 300 mW. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90848 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC
21、FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicita
22、tion or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF D
23、EFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia,
24、 PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No
25、. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence
26、. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements
27、. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The i
28、ndividual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535
29、and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth
30、table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Counting sequence diagram. The counting sequence diagram shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit sh
31、all be as specified on figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90848 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance
32、 characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The
33、electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the
34、entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking
35、 for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535,
36、appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from
37、a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device
38、 classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535,
39、 appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime -VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any ch
40、ange that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation sha
41、ll be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 40 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permi
42、tted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90848 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Gr
43、oup A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOH= -20 A 1, 2, 3 All 4.4 V IOH= -4.0 mA 3.7 Low level output voltage VOLVCC= 4.5 V VIN= VIH= 2.0 V or VIL= 0.8 V IOL= +20 A 1, 2, 3 All 0.1 V IOL= +4.0 mA 0.4 High level input volt
44、age VIHVCC= 4.5 V 2/ 1, 2, 3 All 2.0 V Low level input voltage VILVCC= 4.5 V 2/ 1, 2, 3 All 0.8 V Quiescent supply current ICCVCC= 5.5 V, VIN= VCCor GND IOUT= 0.0 A 1, 2, 3 All 160 A Input leakage current IINVCC= 5.5 V, VIN= VCCor GND 1, 2, 3 All 1.0 A Additional quiescent supply current, TTL inputs
45、 ICCAny one input VIN= 2.4 V or 0.5 V Other inputs VIN= VCCor GND VCC= 5.5 V 1, 2, 3 All 3.0 mA Input capacitance CINVIN= 0 V, see 4.4.1c 4 All 10 pF Power dissipation capacitance 3/ CPDSee 4.4.1c 4 All 63 pF Functional tests See 4.4.1b 7, 8 All Propagation delay time, CPU to TCU tPHL1, tPLH1VCC= 4.
46、5 V CL= 50 pF See figure 5 9 All 27 ns 10, 11 41 Propagation delay time, CPD to TCD tPHL2, tPLH29 All 27 ns 10, 11 41 Propagation delay time, CPU to Qn tPHL3, tPLH3 9 All 40 ns 10, 11 60 Propagation delay time, CPD to Qn tPHL4, tPLH49 All 40 ns 10, 11 60 Propagation delay time, PL to Qn tPHL5, tPLH5
47、9 All 47 ns 10, 11 71 Propagation delay time, MR to Qn tPHL69 All 43 ns 10, 11 65 Transition time 4/ tTHL, tTLH9 All 15 ns 10, 11 22 1/ For a power supply of 5.0 V 10%, the worst case output voltages (VOHand VOL) occur for HCT at VCC= 4.5 V. Thus, the 4.5 V values should be used when designing with
48、this supply. Worst cases VIHand VILoccur at VCC= 5.5 V and 4.5 V, respectively. 2/ Tests are not required if applied as a forcing function for VOHor VOLtests. 3/ Power dissipation capacitance (CPD) determines the dynamic power consumption (PD) and the dynamic current consumption (IS): PD(total) = (CPD+ CL) VCC2f + (VCCx ICC) + (n x d x ICCx VCC) IS= (CPD+ CL) VCC f + ICC+ (n x d x ICC) f is input switching frequency; n is number of inputs switching; d is duty cycle; CLis load capacitance on each output. 4/ This parameter, if not tested, shall be guaranteed to the li
