1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated body of drawing to reflect current requirements. - glg 12-04-20 Charles F. Saffle THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV A A A A A A SHEET 15 16 17 18 19 20 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET
2、 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeff Bowling DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye MICROCIRCUIT,
3、MEMORY, DIGITAL, BICMOS, 16K x 4 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-05-13 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-91593 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E311-12 Provided by IHSNot for ResaleN
4、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting
5、of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.
6、2 Part or Identifying Number (PIN). The complete PIN shall be as shown in the following example: 5962 - 91593 01 M K A | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (s
7、ee 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are m
8、arked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit Access time 01 7B164 16K X 4 SRAM 15 ns 02 7B164 16K X 4 SRAM 12 ns 03 7B164 16K X 4 SRAM 10 n
9、s 04 7B164 16K X 4 SRAM with OE 15 ns 05 7B164 16K X 4 SRAM with OE 12 ns 06 7B164 16K X 4 SRAM with OE 10 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self
10、-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Ou
11、tline letter Descriptive designator Terminals Package style L GDIP3-T24 or CDIP4-T24 24 Dual in-line K GDFP2-F24 or CDFP3-F24 24 Flat pack X CQCC4-N28 28 Rectangular leadless chip carrier Y See figure 1 22 Dual in-line Z See figure 1 22 Rectangular leadless chip carrier 1.2.5 Lead finish. The lead f
12、inish is as specified in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Abs
13、olute maximum ratings. 1/ Supply voltage range to ground potential (VCC) -0.5 V dc to +7.0 V dc DC output current 20 mA Maximum power dissipation 0.800 W Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC): Cases L, K, and X . See MIL-STD-1835 Cases Y and Z 11C/W
14、 2/ Junction temperature (TJ) . +175C Storage temperature range . -65C to +150C Temperature under bias -55C to +125C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage (VIH) 2.2 V dc to VCCVdc Input
15、 low voltage (VIL) -0.5 V dc to 0.8 V dc 3/ Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless o
16、therwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-
17、STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from t
18、he Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the
19、 documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Applications for copies should be addressed to JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) _ 1/ Stresses abov
20、e the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ When thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 3/ VILnegative
21、 undershoots of -3.0 V dc are allowed with a pulse width 3.5 V, IOUT= 0 mA, f = fMAX3/ 1, 2, 3 01,04 50 mA 02,05 55 03,06 60 Input capacitance 4/ CINVCC = 5.0 V, TA = +25C, f = 1 MHz (see 4.4.1e) 4 All 10 pF Output capacitance 4/ COUTVCC = 5.0 VTA = +25C, f = 1 MHz (see 4.4.1e) 4 All 9 pF Functional
22、 tests see 4.4.1c 7,8A, 8B All Read cycle time tAVAVFor timing waveforms, see figure 5. 9, 10, 11 01,04 15 ns 02,05 12 03,06 10 Address access time tAVQV9, 10, 11 01,04 15 ns 02,05 12 03,06 10 Chip enable access time tELQV9, 10, 11 01,04 15 ns 02,05 12 03,06 10 Output hold from address change tAVQX9
23、, 10, 11 All 3 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. E
24、lectrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Chip enable to output active 4/ tELQXFor timing waveforms, see figure 5. 9, 10, 11 01,04 3 ns 02,03 05,06 2 Chip dis
25、able to output inactive 4/ 5/ tEHQZ9, 10, 11 01,04 7 ns 02,05 6 03,06 5 Output enable to output valid tOLQV9, 10, 11 04 6 ns 05,06 5 Output enable to output active 4/ tOLQX9, 10, 11 04-06 2 ns Chip select to output inactive 4/ 5/ tEHQZ9, 10, 11 04 7 ns 05 6 06 5 Write cycle time tAVAV9, 10, 11 01,04
26、 15 ns 02,05 12 03,06 10 Chip enable to write end 5/ tELWH 9, 10, 11 01,04 10 ns 02,03 05,06 8 Address setup to end of write tAVWH 9, 10, 11 01,04 10 ns 02,03 05,06 8 Address setup to write start tAVWL 9, 10, 11 All 0 ns Write recovery time tWHAX 9, 10, 11 All 0 ns Write enable pulse width tWLWH 9,
27、10, 11 01,04 10 ns 02,03 05,06 8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 AP
28、R 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TC+125C 4.5 V VCC 5.5 V Group A subgroups Device types Limits Unit unless otherwise specified Min Max Data setup to write end tDVWH For timing waveforms, see figure 5. 9, 10, 11 01,04 7 ns 02,05 6 03,06
29、5 Data hold from write end tWHDX 9, 10, 11 All 0 ns Write enable high to output active 3/ 6/ tWHQX9, 10, 11 01,04 3 ns 02,03, 05,06 2 Write enable low to output inactive 3/ 6/ tWLQZ9, 10, 11 01,04 7 ns 02,05 6 03,06 5 1/ AC tests are performed with input rise and fall times of 3 ns or less, timing r
30、eference levels of 1.5 V, input pulse levels of 0 V to 3.0 V, and the output load in figure 4, circuit A. 2/ These are absolute values with respect to device ground and all overshoots and undershoots due to system or tester noise are included. 3/ At f = fMAX, address and data inputs are cycling at t
31、he maximum frequency of 1/tAVAV. 4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the limits specified in table I. 5/ Transition is measured at steady state-high level -200 mV or steady state low level +200 mV on the output
32、from the 1.5 V level on the input, CL= 5 pF (including scope and jig). See figure 4, circuit B. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION L
33、EVEL A SHEET 8 DSCC FORM 2234 APR 97 Case Y Symbol Inches Millimeters Min Max Min Max A .155 .200 3.94 1.68 B .015 .020 .038 1.98 B2 .045 .065 1.14 7.42 C .009 .012 0.23 7.82 D 1.060 1.110 26.92 9.96 E .100 BSC 2.54 BSC eA .360 BSC 9.14 BSC E .245 .310 6.22 7.87 E1 .290 .320 7.37 8.13 L .125 .200 3.
34、18 5.08 Q .015 .060 0.38 1.52 S .060 .095 1.52 2.41 S1 .005 0.13 3 15 FIGURE 1. Case outlines. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE
35、VEL A SHEET 9 DSCC FORM 2234 APR 97 Case Z Symbol Inches Millimeters Min Max Min Max A .060 .075 1.52 1.91 A1 .050 .066 1.27 1.68 B .022 .028 .056 .071 B1 .045 .055 1.14 1.40 B2 .020 .050 0.51 1.27 D .284 .296 7.21 7.52 E .484 .496 12.29 12.60 L1 .045 .050 1.14 1.27 L2 .045 .050 1.14 1.27 R .008 REF
36、 0.20 REF FIGURE 1. Case outlines - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 Device type
37、s 01-03 04-06 Case outlines Y, Z K L, K X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A A A A A A A A A CE GND WE I/O I/O I/O I/O A A A A A VCC- - - - - - A A A A A A A A A CE NC GND WE I/O I/O I/O I/O NC A A A A A VCC- - - - A A A A A A
38、 A A A CE OE GND WE I/O I/O I/O I/O NC A A A A A VCC- - - - NC NC A A A A A A A A A CE OE GND NC WE I/O I/O I/O I/O NC A A A A NC NC VCCFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE
39、 A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 11 DSCC FORM 2234 APR 97 Device types 01 - 03. CEWEInputs/Outputs Mode H L L X H L High Z Data out Data in Deselect/Powerdown Read Write Device types 04 - 06. CEWEOE Inputs/Outputs Mode H L L L X H L H X L X H High
40、Z Data out Data in High Z Deselect/Powerdown Read Write Deselect FIGURE 3. Truth tables. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A
41、SHEET 12 DSCC FORM 2234 APR 97 Note: Including scope and jig (minimum values). AC test conditions Input pulse levels Input rise and fall times Input timing reference levels Output reference levels GND to 3.0 V 3 ns 1.5 V 1.5 V FIGURE 4. Output load circuit and test conditions. Provided by IHSNot for
42、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 13 DSCC FORM 2234 APR 97 Notes: 1. Device is continually selected, CE = VIL. For device types 04-06 only,
43、 OE = VIL. 2. WEis held high during read cycles. 3. Address valid prior to or coincident with CE transition low. 4. Device types 04-06 only. FIGURE 5. Timing waveform diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW
44、ING SIZE A 5962-91593 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 14 DSCC FORM 2234 APR 97 Notes: 1. The internal write time of the memory is defined by the overlap of CE low and WE low. Both signals must be low to initiate a write and either signal can terminate a write b
45、y going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 2. For device types 04-06 only, data I/O will be high-impedance if OE = high. 3. If CE goes high simultaneously with WE high, the output remains in a high-impedance sta
46、te. 4. During this period the I/O pins are in the output state, and input signals should not be applied. 5. If the CE low transition occurs after the WE transition the output remains in a high-impedance state. FIGURE 5. Timing waveform diagrams - continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-
