1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Make change to “VREFHto VREFL” limits as specified in 1.3 and add functional test to table I. - ro 01-06-05 R. Monnin B Redraw. Update drawing to current requirements. - drw 12-03-22 Charles F. Saffle REV SHEET REV SHEET REV STATUS REV B B B B B
2、B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra B. Rooney DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT
3、 OF DEFENSE CHECKED BY Charles E. Besore APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL-LINEAR, 12-BIT, QUAD, D/A CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-05-20 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-91764 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E117-12 Provided by I
4、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class l
5、evels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflecte
6、d in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 91764 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. D
7、evice classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates
8、a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function Output registers on reset (see figure 2) 01 DAC8412A Quad, voltage output, 12-bit Midscale BiCMOS DAC with readback 02 DAC8412B Quad, voltage output, 12-bit Mi
9、dscale BiCMOS DAC with readback 03 DAC8413A Quad, voltage output, 12-bit Zero scale BiCMOS DAC with readback 04 DAC8413B Quad, voltage output, 12-bit Zero scale BiCMOS DAC with readback 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance le
10、vel as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The
11、case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T28 or CDIP2-T28 28 Dual-in-line 3 CQCC1-N28 28 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q
12、and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3
13、Absolute maximum ratings. 1/ VSSto VDD-0.3 V dc, +33.0 V dc VSSto VLOGIC. -0.3 V dc, +23.5 V dc VSSto DGND . -16. 5 V dc VDDto DGND +16.5 V dc VLOGICto DGND . -0.3 V dc, +7.0 V dc VSSto VREFL. -0.3 V dc, VDD 2.0 V dc VREFHto VDD+2.0 V dc, +33.0 V dc VREFHto VREFL0 V dc, VDD VSSCurrent into any pin 1
14、5 mA Digital input voltage to DGND -0.3 V dc, VLOGIC+ 0.3 V dc Digital output voltage to DGND -0.3 V dc, +7.0 V dc Power dissipation (PD) . 1000 mW 2/ Junction temperature (TJ) +150C Storage temperature range -65C to +150C Lead temperature (soldering, 60 seconds) +300C Thermal resistance, junction-t
15、o-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case X 50C/W Case 3 70C/W 1.4 Recommended operating conditions. Supply voltage range . 15 V dc Logic supply voltage (VLOGIC) . +5 V dc Positive reference voltage range (+VREF) . +2.5 V dc to +10.0 V dc Negative reference volt
16、age range (VREF) -10.0 V dc to 0 V dc Ground potential 0 V dc Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifi
17、ed herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard
18、Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derate above +80C at 14.3 mW/C fo
19、r case 3. Derate above +100C at 20 mW/C for case X Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 DEPARTME
20、NT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, P
21、hiladelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has
22、been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect t
23、he form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physica
24、l dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as spec
25、ified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Block diagram. The block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical perfor
26、mance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each sub
27、group are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marki
28、ng the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance ma
29、rk. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be
30、required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The
31、 certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MI
32、L-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot f
33、or ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C
34、 TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Integral linearity INL 1, 2, 3 01, 03 -0.75 +0.75 LSB 02, 04 -1.5 +1.5 Differential linearity DNL 1, 2, 3 All -1.0 +1.0 LSB Minimum scale error VZSERL 2 k 1, 2, 3 All -2.0 +2.0 LSB Full scale error VFSERL 2 k 1, 2
35、, 3 All -2.0 +2.0 LSB Linearity matching TA= +25C 1 All -1.0 +1.0 LSB Minimum scale offset matching TA= +25C 1 All -1.0 +1.0 LSB Full scale offset matching TA= +25C 1 All -2.0 +2.0 LSB Reference input current IREFHCode 555H& 000H1, 2, 3 All -2.75 +2.75 mA IREFL0 +2.75 Output voltage swing VOUT (MIN)
36、 RL= 2 k 1, 2, 3 All -10.0098 -9.9902 V VOUT (MAX) +9.9853 +10.0048 Logic input high voltage VINH1, 2, 3 All 2.4 V Logic input low voltage VINL1, 2, 3 All 0.8 V Logic output high voltage VOHIOH= +0.4 mA 1, 2, 3 All 2.4 V Logic output low voltage VOLIOL= -1.6 mA 1, 2, 3 All 0.4 V Logic input current
37、IINVIN= 0 V or + 5 V 1, 2, 3 All 10 A Power supply sensitivity PSS 14.25 V VDD 15.75 V 1, 2, 3 All 150 ppm/V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND M
38、ARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Positive supply current IDDVREFH= +2.5 V 1,
39、 2, 3 All 13 mA Negative supply current ISS1, 2, 3 All -10 mA Logic supply current ILOGIC1, 2, 3 All 100 A Slew rate SR Measured at 10 % to 90 %, TA= +25C, VO= 0 V to 10 V 2/ 4 All 2 V/s Functional test FT See 4.4.1c 7 All Settling time tS10 V step to 0.01 %, 2/ TA= +25C 9 All 15 s Chip select write
40、 pulse width tWCS2/, 3/ 9, 10, 11 All 90 ns Write setup tWStWCS= 90 ns 2/, 3/ 9, 10, 11 All 0 ns Write hold tWHtWCS= 90 ns 2/, 3/ 9, 10, 11 All 0 ns Address setup tAS2/, 3/ 9, 10, 11 All 0 ns Address hold tAH2/, 3/ 9, 10, 11 All 0 ns Load setup tLS2/, 3/ 9, 10, 11 All 70 ns WRITE load hold tLH2/, 3/
41、 9, 10, 11 All 30 ns WRITE data setup tWDStWCS= 90 ns 2/, 3/ 9, 10, 11 All 20 ns WRITE data hold tWDHtWCS= 90 ns 2,/ 3/ 9, 10, 11 All 0 ns Load pulse width tLWD2/, 3/ 9, 10, 11 All 170 ns Reset pulse width tRESET2/, 3/ 9, 10, 11 All 200 ns Chip select read pulse width tRCS2/, 3/ 9, 10, 11 All 130 ns
42、 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical perform
43、ance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Read data hold tRDHtRCS= 130 ns 2/ 3/ 9, 10, 11 All 0 ns Read data setup tRDStRCS= 130 ns 2/ 3/ 9, 10, 11 All 10 ns Data to high Z tDZRL= 3 k, 2/ 3/ CL
44、= 10 pF 9, 10, 11 All 200 ns Chip select to data tCSDRL= 3 k, 2/ 3/ CL= 100 pF 9, 10, 11 All 200 ns 1/ All supplies can be varied 5 % and operation is guaranteed. Unless otherwise specified, VDD= +15 V, VSS= -15 V, VLOGIC= +5 V, VREFH= +10 V, and VREFL= -10 V. 2/ Guaranteed by characterization and n
45、ot 100 % tested. 3/ All input control signals are specified with tr= tf= 5 ns (10 % to 90 % of +5 V) and timed from a voltage level of 1.6 V. See figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-9176
46、4 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device types 01, 02, 03, 04 Case outlines X and 3 Terminal number Terminal symbol 1 VREFH2 VOUTB3 VOUTA4 VSS5 DGND 6 RESET 7 LDAC 8 DB0 (LSB) 9 DB1 10 DB2 11 DB3 12 DB4 13 DB5 14 DB6 15 DB7 16 DB8 17 DB9
47、 18 DB10 19 DB11 (MSB) 20 R / W 21 A1 22 A0 23 CS 24 VLOGIC25 VDD26 VOUTD27 VOUTC28 VREFLFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91764 DLA LAND AND MARITIME COLUMBUS, O
48、HIO 43218-3990 REVISION LEVEL B SHEET 9 DSCC FORM 2234 APR 97 A1 A0 R / W CS RS LDAC Input reg Output reg Mode DAC L L L L H L Write Write Write A L H L L H L Write Write Write B H L L L H L Write Write Write C H H L L H L Write Write Write D L L L L H H Write Hold Write input A L H L L H H Write Hold Write input B H L L L H H Write Hold Write input C H H L L H H Write Hold Write input D L L H L H H Read Hold Read
