1、LTR I I I DESCRIPTION DATE (YR-MO-DA) APPROVED REV I l l SHEET REV I I SHEET REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA DESC FORM 193 JUL 94 REV SHEET PREPARED BY Thanh V. Nguyen
2、CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 96-06-1 2 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, FAST CMOS, 20-BIT NONINVERTING BUFFER/LINE DRIVER WITH CURRENT LIMITING RESISTORS AND INPUTS AND LIMITEDOUTPUT VOLTAGE
3、SWING, MONOLITHIC SILICON THREE-STATE OUPTPUTS, lTL COMPATIBLE SIZE CAGE CODE A I67268 I 5962-92281 _ SHEET 1 OF 17 5962-E451-96 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from
4、 IHS-,-,-SND-5962-9228L 9999996 0088539 84T 1. SCOPE 1.1 u. This drawing docunents two product assurance class levels consisting of high reliability (device classes P and M) and space application (device class V). and are reflected in the Part or Identifying Number (PIN). (RHA) levels are reflected
5、in the PIN. A choice of case outlines and lead finishes are available When available, a choice of Radiation Hardness Assurance 1.2 pIIi1. The PIN is as shown in the following example: 92281 Federal RHA Ill1 Device Device Case Lead Il stock class designator type class outline finish designator (see 1
6、.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) LL (see 1.2.3) V Drawing nunber 1.2.1 RHA desimator. Device classes P and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. . Lead temperature (soldering, seconds) Therm 1 res i st
7、ance, junction- to- case (8 Jc) . Junction tenperature (TJ) Maxim power dissipation (PD) . 1.4 Recmnded omratins conditions. 2J 3/ Supply voltage range (Vc ) . Input voltage range (vIN$ Output voltage range (IwT) . Maximum low level input voltage (VIL) Minimun high level input voltage (VI,) . Case o
8、perating temperature range (TC) Maximan input rise or fall rate (At/AV): Maximum high level output current (IOH) . Maximum low level output current (IoL) . (from VIR = 0.3 V to 2.7 v, 2.7 V to 0.3 V) 1.5 Disital losic testins for device classes P and V. STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRO
9、NICS SUPPLY CENTER DAYTON, OHIO 45444 -0.5 V dc to +7.0 V dc -0.5 V dc to Vcc + 0.5 V dc -0.5 V dc to Vcc -20 mA I20 tn4 -30 tn4 +70 mA 1480 tn4 +I120 mA -65C t +150“C -65C to +135C 4/ +300*C See MIL-STO-1835 +175C 1.0 u SIZE A 5962-92281 REVISION LEVEL SHEET 3 +4.5 V dc to +5.5 V dc +O.O V dc to Vc
10、c +O.O V dc to Vcc 0.8 V 2.0 v -55C to +125C 2.5 ns/V -16 mA 16 mA Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) XX percent s/ 2. APPLICABLE DOCUMENTS 2.1 Government swcification. standards. and handbooks. The following specification, standards, and handbook
11、s form a part of this drawing to the extent specified herein. those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solitation. Unless otherwise specified, the issues of these docunents are SPECIFICATION MI LITARY M
12、IL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. maxim levels may degrade performance and affect reliability. Extended operation at the 2/ Unless otherwise noted, all voltages are ref
13、erenced to GND. 2/ lhe limits for the parameters specified herein shall apply over the full specified Vcc range and case temperature range of -55C to +125“C. hall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to qual :onformance inspection. 4.2.1 Addit
14、ional criteria for device class M. a. Burn-in test, method 1015 of MIL-STO-883. lbe screen i ng tY (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under docunent revision level control and shall be made available to the preparing or acquiring activity upon
15、request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance uith the intent specified in test method 1015. (2) TA = +125C, minim. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 4. a. The bur
16、n-in test duration, test condition and test temperature, or approved alternatives shall be as specifiec in the device manufacturers PM plan in accordance uith MIL-PRF-38535. maintained under document revision level control of the device manufacturers Technology Review Board (TRB) ii accordance with
17、MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. The burn-in test circuit shall b
18、e b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class P shall be as specified in MIL-PRF-38535, appendix E. 4.3 Qualification insrxction for device classes P and V. Qualification
19、inspection for device classes Q and V shal Inspections to be performed shall be those specified in MIL-PRF-38535 and herei be in accordance with MIL-PRF-38535. for groups A, B, C, O, and E inspections (see 4.4.1 through 4.4.4). 4.3.1 Electrostatic discharse sensitivity aualification insrmtion . test
20、ing shall be performed in accordance with MIL-STD-883, method 3015. initial qualification and after process or design changes which may affect ESDS classification. Electrostatic discharge sensitivity (ESDS) ESDS testing shall be measured only for STANDARD I SIZE A REVISION L MICROCIRCUIT DRAWING DEF
21、ENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 EVEL I SHEET DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-9228Z 9999996 0088523 270 mM= moEz = For all other 2.0 V or 0.8 V i nputs VIN = Vcc or GND vOUT = vCc VOUT =
22、 GND TABLE I. Electrical Derformance Characteristics. Test conditions 2/ -55C i TC s +125C unless otherwise specified +4.5 v s vp i +5.5 v Group A subgroups Limits I/ Unit Test and test method 1/ MIL-STD-883 Min I Max V High level output voltage 3006 IOH = -300 /LA For all inputs affecting output un
23、der test OH2 VIN = 2.0 V or 0.8 V Low level output vo 1 tage 3007 V For all other inputs VIN = Vcc or GND VOL2 IOL = 16 In4 Negative input clamp voltage 3022 For input under test, IIN = -18 mA V VI c- All 4.5 V ALL 5.5 V ALL 5.5 V All 5.5 V ALL 5.5 V All 5.0 V All 5.0 V All 5.5 V All 5.5 V ALL 5.5 V
24、 ALL 5.5 V Three-state output leakage current high 3021 Three-state output leakage current 1 ow 3020 3010 Input current high IIH for input under test, VIN = Vcc for all other inputs, VIN = V or G6S FA input current low 3009 IIL IrA for input under test, VIN = GND For all other inputs, VIN = V VIN =-
25、2.0 V or 0.8 V VIN = 2.0 V or 0.8 V VOuT = 1.5 V Gib Or VOuT - 1.5 v In4 Output current low 301 1 Output current high 301 1 Dynamic power supply current 15% Outputs open FA/ MHz4 i t Quiescent supply current delta, TTL input Level 3005 gcc For input under test For all other inputs VIN = Vcc or GND m
26、m = mm = GND For all other inputs VIN = Vcc or GND VIN = 3.4 v Quiescent supply current, outputs high 3005 ICCH Quiescent supply current, outputs LOW 3005 ICCL See footnotes at end of table. 5962-92281 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444
27、DESC FORM 19% JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- SMD-5962-92281 9979996 OO52L) 107 TABLE I. Electrical Derformance characteristics - Continued. CC Group A Limits z/ Unit subgroups 5.5 v 5.5 V 5.5 V Min 1, 2, 3 4, 5, 6 4, 5, 6 4,
28、5, 6 4, 5, 6 - 5.5 - 20.5 6.0 8.0 - - H H 9.0 6.5 5 .O 17.0 14.0 11.0 pF pF mV mV ns GND GND 5.0 V 5.0 V 4.5 V 5.5 v 4.5 V 4 4 4 4 4 4 7, 8 L 7, 8 L 9, 10, 11 1.5 9, 10, 11 1.5 REVISION LEVEL SHEET 7 Test and test method 1/ MI L -STO-883 ievice type - Al 1 - Al 1 - ALL - Al 1 - AL 1 - Al 1 Test cond
29、itions z/ -55C i TC i +125“C unless otherwise specified +4.5 v 5 va L +5.5 v Max I f $cz nOEl= moE2 = vCc For all other inputs VIN = Vcc or GND Quiescent supply current, outputs disabled 3005 Total supply current 3utputs ope2 DOEI = mOE2 = GND One bit toggling 5b% duty cycle For nonswitching f- = IO
30、 MHz For switching inputs IN = : and the absolute value of the magnitude, not the sign, is relative to the minim and maximum limits, as applicable, listed herein. limits specified in table I at 4.5 V i Vcc L 5.5 V. b/ This parameter is guaranteed, if not tested, to the limits specified in table I he
31、rein. y Three-state output conditions are required. u This test may be performed using VI, = 3.0 V. When VIH = 3.0 V is used, the test is guaranteed for VIH = 2.0 V. 7/ Not more than one output should be tested at a time. B/ Icm may be verified by the following equation: ICCD = uhere ICCT, Icc (Icc
32、or ICCH in table I), and AI device under test, wken tested as described in tab? I, herein. The values for D, NT, fCp, fi, and Ni shall be as listed in the test conditions colm for ICCT 3/ All devices shall meet or exceed the The duration of the test should not exceed one second. CCT - CC - DHNTAICC
33、fCpI2 + fiNi shall be the measured values of these parameters, for the in table I, herein. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical Derformance characteristics - Continued. f This test may be performed
34、 either one input at a time (preferred method) or with all input pins simultaneously at IN = RC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using t e alternate test method, the maximum limit is equal to the nunber of inputs at a high TTL inp
35、ut level times 1.5 m4; and the preferred method and limits are guaranteed. 3/ ICCT is calculated as follows: STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 where I Df= Duty cycle for TTL inputs at 3.4 V NT = Nunber of TTL inputs at 3.4 V :Icc-= Quiescent supply cu
36、rrent delta, TTL inputs at 3.4 V fEF=-Clock frequency for registered devices (fCp O for nonregistered devices) fi = Input frequency Ni = Nunber of inputs at fi = Quiescent supply current (any IccL or ICCH) Dynamic power supply current caused by an input transition pair (HLH or LHL) IJ This test is r
37、equired only for group A testing; see 4.4.1 herein. z/ This test is for qualification only. Ground and V bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of ingced noise caused by other sinultaneously switching outputs. The test is performed on a
38、 low noise bench test fixture. with 5000 of load resistance and a minim of 50 pF of load capacitance (see figure 4). resistors shall be used. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. shall be placed in parallel from Vcc to ground. the device manufactur
39、er. The low and high level ground and V a 1 GHz minim bandwidth oscilloscope with a 50a input impet%nce. The device inputs shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then be conditioned such that they switch simultaneously and the output under
40、 test remains at V other outputs possible are switched from VOH to VOL. VOHV and VOHP are then measured from the nomina7 VOH level to the largest negative and positive peaks, respectively (see figure 4). outputs not under test switching from VOL to VoH. The device inputs shall be conditioned such th
41、at all outputs are at a low nominal VOL level. shall then be conditioned such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VOL to VOH. VoLp and VoLv are then measured from the nominaPLVOL levei to the largest positive and negative pe
42、aks, respectively (see figure 4). outputs not under test switching from VOH to VOL. The V shall% added by revision no more than 90 days from the date of this drawing. For the device under test, all outputs shall be loaded The output load components shall be located as close as possible to the device
43、 outputs. The values of these decoupling capacitors shall be determined by Only chip capacitors and DecoupLing capacitors bounce noise is measured at the quiet output using as all This is then repeated with the same The device inputs as all This is then repeated with the same and ground bounce tests
44、 were not completed at the date of this drawing. The limits for these parameters i/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and All possible input to output logic patterns per function other logic patterns used for fault detection. m
45、inim, test all functions of each input and output. shall be guaranteed, if not tested, to the truth table in figure 2 herein. sequence as approved by the qualifying activity on qualified devices. AC limits at Vc 5.5 V are equal to the limits at Vcc = 4.5 V and guaranteed by testing at V = 4.5 V. Min
46、im propagation de ay time limits for Vc = 4.5 V and 5.5 V are guaranteed, if not tested, to the ffmits specified in table I, herein. The limits at Vcc = 5.5 tS (o) is the absolute value of the difference between thc The test vectors used to verify the truth table shall, at a FunctionaL tests shall b
47、e perfod ir For outputs, L 1.5 V, H a 1.5 V. For propagation defay tests, all paths must be tested. Is/ This parameter is guaranteed, if not tested, to the limits specified in table I herein. are guaranteed and equal to the limits at Vcc = 4.5 V. actual propagation delay for any two separate outputs
48、 of tke same package switching in the same direction (low-to-high, high-to-low). SIZE A 5962-92281 REVISION LEVEL SHEET 9 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-9228L 9999996 0088527 9Lb Terminal symbol mAn (m = 1 to 2, n = 1 to IO)
49、 mYn (m = 1 to 2, n = 1 to IO) mM, moEz (m = i to 2) Device types Description Data inputs Three-state outputs Output enable control inputs (active low) Case outline Terminal nunber 1 2 3 4 5 6 7 8 9 10 11 12 13 14 01, 02, 03 X Termina 1 symbol 10E1 lY1 1Y2 GND 1 Y3 1Y4 vcc 1Y5 1Y6 1Y7 GND 1Y8 1Y9 1Y10 Terminal number 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Terminal Symbol 2Y1 2Y2 2Y 3 GND 2Y 4 2Y5 2Y6 vcc 2Y7 218 GND 2Y 9 2Y10 2m Ter
