1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to meet current MIL-PRF-38535 requirements. - glg 13-09-30 Charles Saffle REV SHEET REV A A A A A A A A A SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
2、PMIC N/A PREPARED BY Rajesh Pithadia DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Kenneth Rice COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASABLE,
3、 PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL 93-10-22 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-93248 SHEET 1 OF 23 DLA Land and Maritime FORM 2233 APR 97 5962-E559-13 .Provided by IHSNot for ResaleNo reproduction or networking
4、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93248 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device c
5、lasses Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in
6、 the following example: 5962 - 93248 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Device type(s). The device type(s) identify the circuit functi
7、on as follows: Device type Generic number Circuit function tPD01 V5000 60-input 52-output AND-OR-logic array 25 ns 02 V5000 60-input 52-output AND-OR-logic array 35 ns 03 V5000L 60-input 52-output AND-OR-logic array 35 ns 1.2.2 Device class designator. The device class designator is a single letter
8、identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL
9、-PRF-38535 1.2.3 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA3-P68 68 1/ pin grid array 2/ Y GQCC1-J68 68 “J” leaded chip carrier 2/ 1.2.4 Lead finish. The lead finish is as specified in MI
10、L-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 3/ 4/ Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range . -2.0 V dc to +7.0 V dc 5/ Output voltage range applied -0.5 V dc to +7.0 V dc 5/ Output sink current . 8 mA Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximu
11、m power dissipation (PD) 6/ 1.2 W Maximum junction temperature. +175C Lead temperature (soldering, 10 seconds maximum) . +300C Data retention . 10 years (minimum) Endurance 25 erase/write cycles (minimum) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,
12、-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93248 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.5 V dc to 5.5 V dc Supply voltage (VSS) . 0.0 V dc High level input voltage (VIH). 2.
13、0 V dc minimum Low level input voltage (VIL) 0.8 V dc maximum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specifie
14、d herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard M
15、icrocircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or fr
16、om the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of t
17、he documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be add
18、ressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington,
19、VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the eve
20、nt of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ 68 = actual number of pins used, not the max
21、imum listed in MIL-STD-1835. 2/ Lid shall be transparent to permit ultraviolet light erasure. 3/ Stresses above the absolute maximum value may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ All voltages referenced to
22、VSS. 5/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 6/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for
23、 ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93248 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be
24、in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to M
25、IL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifica
26、tions shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimension
27、s. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.3 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth
28、 table(s). 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2), the device shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the to
29、tal number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.2.4 Logic block diagram. The logic diagram s
30、hall be as specified on figure 2. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical tes
31、t requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may
32、 also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in
33、 compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPLDS. All testing requirements and quality assurance provisions herein shall
34、be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.6. 3.6.2 Programmability of EPLDS. When specified, devices shall be programmed to the specified pattern using the p
35、rocedures and characteristics specified in 4.7. 3.6.3 Verification of erasure of programmability of EPLDs. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verif
36、y that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Processing EPLDs. Since the device is capable of being programmed by the manufacturer or the user to result in a wide variety of c
37、onfigurations; two processing options are provided for selection in the contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93248 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5
38、 DSCC FORM 2234 APR 97 3.7.1 Unprogrammed device delivered to the user. All testing shall be verified through Group A testing as defined in 3.2.3.1 and Table IIA. It is recommended that users perform subgroup 7 and 9 after programming to verify the specific program configuration. 3.7.2 Manufacturer
39、programmed device delivered to the user. All testing shall be verified through Group A testing as defined in 3.2.3.1 and Table IIA. It is recommended that users perform subgroup 7 and 9 after programming to verify the specific program configuration. 3.8 Certificate of compliance. A certificate of co
40、mpliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meet
41、s the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.9 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.10 Notification of change. Notification of
42、change to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.11 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. O
43、ffshore documentation shall be made available onshore at the option of the reviewer. 3.12 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors. This reprogrammability test shall be done for initial characterization and after any design or process changes
44、 which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control
45、 and shall be made available upon request of the acquiring or preparing activity, along with test data. 3.13 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or proce
46、ss change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon req
47、uest of the acquiring or preparing activity, along with test data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93248 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234
48、 APR 97 TABLE I. Electrical performance characteristics Test Symbol Conditions 1/ VSS= 0 V 4.5 V VCC 5.5 V -55C TC +125C Unless otherwise specified Group A Subgroups Device types Limits Unit Min Max High level output voltage VOHVCC= 4.5 V, VIL= 0.8 V, IO= - 4.0 mA VIH= 2.0 V 1,2,3 All 2.4 V Low level output voltage VOLVCC= 4.5 V, VIL= 0.8 V, IO= 6.0 mA VIH= 2.0 V 1,2,3 All 0.5 V High impedance 2/ output leakage current IOZVCC= 5.5 V 1,2,3 All -10 10 uA High level input current IIHVIH= -0.1 V to VCC= -1.0 V 1,2,3 All 10 uA Low level input current IILVIL= -0.1 V to VCC= -1.0 V 1
