1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED F Added device type 11. Added vendor CAGE code 0EU86 for device types 05 through 09. -sld 99-09-07 Raymond Monnin G Add note to paragraph 1.2.2 and table I, conditions. Add case outline 9. 00-04-06 Raymond Monnin H Correct figure 1, case outline M
2、diagram, adding dimension “c“, lead thickness. Change figure 1, case outline M, A2 maximum dimension from 0.015“ to 0.025“ and clarify A2 dimension in note 3. 00-06-14 Raymond Monnin J Figure 1, case outline 9; changed the min limit for dimensions D2/E2 from 0.990 inches to 0.980 inches. Added vendo
3、r cage 88379 for the case outline 9. Updated paragraph 1.2.3 to describe the five class levels. -sld 01-05-06 Raymond Monnin K Added device types 12 through 18. -sld 01-11-14 Raymond Monnin L Added case outline A -sld 03-02-21 Raymond Monnin M Added case outline B. Added note to paragraph 1.2.4. -sl
4、d. 03-09-22 Raymond Monnin N Re-inserted case outline 9 drawing to figure 1. -sld. 04-01-07 Raymond Monnin REV SHEET REV N N N N N N N N N N N N N N N SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS REV N N N N N N N N N N N N N N OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N
5、/A PREPARED BY Steve L. Duncan DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael C. Jones COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, DIGITAL, STATIC RAND
6、OM ACCESS MEMORY, CMOS, 128K x 32-BIT AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-07-19 AMSC N/A REVISION LEVEL N SIZE A CAGE CODE 67268 5962-95595 SHEET 1 OF 29 DSCC FORM 2233 APR 97 5962-E101-04 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited
7、. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five
8、product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The
9、 PIN shall be as shown in the following example: 5962 - 95595 01 H A X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) de
10、signator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type 1/ Generic number Circui
11、t function Access time 01 128K32-120 SRAM, 128K x 32-BIT 120 ns 02 128K32-100 SRAM, 128K x 32-BIT 100 ns 03 128K32-85 SRAM, 128K x 32-BIT 85 ns 04 128K32-70 SRAM, 128K x 32-BIT 70 ns 05,12 128K32-55 SRAM, 128K x 32-BIT 55 ns 06,13 128K32-45 SRAM, 128K x 32-BIT 45 ns 07,14 128K32-35 SRAM, 128K x 32-B
12、IT 35 ns 08,15 128K32-25 SRAM, 128K x 32-BIT 25 ns 09,16 128K32-20 SRAM, 128K x 32-BIT 20 ns 10,17 128K32-17 SRAM, 128K x 32-BIT 17 ns 11,18 128K32-15 SRAM, 128K x 32-BIT 15 ns 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance leve
13、l. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available.
14、This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening
15、 and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C and D). 1/ Due to the nature of the 4 transistor design of the die used in these device
16、types, topologically pure testing is important, particularly for high reliability applications. The device manufacturer should be consulted concerning their testing methods and algorithms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR
17、OCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 3 DSCC FORM 2234 APR 97 E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) mus
18、t be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified f
19、low. This product may have a limited temperature range. 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A See figure 1 68 Co-fired ceramic, single cavity, quad flat pack B See figure 1 68
20、Ceramic, quad flatpack M 1/ 2/ See figure 1 68 Ceramic, quad flatpack, single/dual cavity N See figure 1 68 Co-fired ceramic, single cavity, ultra low profile, quad flat pack X See figure 1 68 Ceramic, quad flatpack Y See figure 1 68 Ceramic, quad flatpack, low profile Z See figure 1 68 Ceramic, qua
21、d flatpack, dual cavity 9 2/ See figure 1 68 Ceramic, quad flatpack 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Signal voltage range (any pin) -0.5 V dc to +7.0 V dc Power dissipation (P
22、D): Device types 01 through 08, and 12 through 15 2.75 W maximum Device types 09, 10, 11, 16, 17, and 18 3.30 W maximum Thermal resistance junction-to-case (JC): Case outlines X and Y. 6.6C/W Case outline M. 10C/W Case outlines A and N. 2.72C/W Case outline Z . 8C/W Case outlines B and 9 . 4.9C/W St
23、orage temperature. -65C to +150C Lead temperature (soldering, 10 seconds) . +300C 1.4 Recommended operating conditions. Supply voltage (VCC) . +4.5 V dc to +5.5 V dc Input low voltage range (VIL). -0.3 V dc to +0.8 V dc Input high voltage range (VIH) . +2.2 V dc to VCC+0.5 V dc Output low voltage, m
24、aximum (VOL) +0.4 V dc Output high voltage, minimum (VOH). +2.4 V dc Case operating temperature range (TC) -55C to +125C 1/ The case outline M is available in either a single or dual cavity package. 2/ Due to the short leads of case outlines M (single cavity) and case outline 9, caution should be ta
25、ken if the system application is to be used where extreme thermal transitions can occur. Case outline A can be used if longer leads are necessary. 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance
26、and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.
27、1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specif
28、ications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard
29、Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document
30、 Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. Nothing in this document , however, supercedes applicable
31、laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tes
32、ts herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. Therefore, the tests and inspections herein may not be performed for the applicable device class (see MIL-PRF-38534). Furthermore, the manufacturer may take exception
33、s or use alternate methods to the tests and inspections herein and not perform them. However, the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions sh
34、all be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on
35、 figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5. 3.2.5 Block diagram(s). The block diagram(s) shall be as specified on figure 6. 3.2.6 Output load circuit. The output load circuit shall be as specified on figure 7. Provided by IHSNot for ResaleNo re
36、production or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 5 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the e
37、lectrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described
38、 in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marked as listed in MIL-HDBK-103 and QML-38534. 3.6 Data. In addition to
39、the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a su
40、mmary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. 3.7 Certificate of compliance. A certificate of compli
41、ance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate
42、of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COL
43、UMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 1/ 2/ -55C TC +125C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device types Min Max Unit DC parameters Supply cur
44、rent 32-bit mode ICC32CS = VIL, OE = VIH, VCC = +5.5 V dc f = 5 MHz CMOS compatible 1,2,3 01,02 03,04 05-18 120 120 600 mA Standby current ISBCS = VIH, OE = VIH, VCC = +5.5 V dc f = 5 MHz CMOS compatible 1,2,3 01,02 03,04 05-08 12-15 09-11 16-18 2.4 5.0 60 60 80 80 mA Input leakage current ILIVCC= +
45、5.5 V dc, VIN= GND or VCC1,2,3 All 10 A Output leakage current ILOCS = VIH, OE = VIH, VIN= GND or VCC1,2,3 All 10 A VCC= +4.5 V dc, IOL= 2.1 mA 01-07, 12-14 0.4 Output low voltage VOLVCC= +4.5 V dc, IOL= 8 mA 1,2,3 08-11, 15-18 0.4 V VCC= +4.5 V dc, IOL= -1.0 mA 01-07, 12-14 2.4 Output high voltage
46、VOHVCC= +4.5 V dc, IOL= -4.0 mA 1,2,3 08-11, 15-18 2.4 V Data retention characteristics Data retention supply voltage VDRCS VCC - 0.2 V dc 1,2,3 All 2.0 5.5 V 01-04 1.6 05-11 11.6 Data retention current ICCDR1VCC= 3 V dc 1,2,3 12-18 20.0 mA See footnotes at end of table. Provided by IHSNot for Resal
47、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95595 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL N SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbo
48、l Conditions 1/ 2/ -55C TC +125C VSS= 0 V dc +4.5 V dc VCC +5.5 V dc unless otherwise specified Group A subgroups Device types Min Max Unit Capacitance OE capacitance 3/ COEVIN= 0 V dc, f = 1.0 MHz, TA = +25C 4 All 50 pF VOUT= 0 V dc, f = 1.0 MHz, TA = +25C, Case outlines X and Y 50 WE capacitance 3/ CWEVOUT= 0 V dc, f = 1.0 MHz, TA = +25C, Case outlines A, B, M, N, Z, and 9 4 All 20 pF CS capacitance 3/ CCSVIN= 0 V dc, f = 1.0 MHz, TA = +25C 4 All 20 pF D0-31capacitance 3/ CI/OVOUT= 0 V dc, f = 1.0 MHz, TA = +25C
