1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to meet current requirements. -rrp 01-08-13 R. Monnin B Redrawn. Drawing format and paragraphs updated to MIL-PRF-38535 requirements. - drw 12-12-18 Charles F. Saffle REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B O
2、F SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Marcia B. Kelleher DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY
3、Rajesh Pithadia APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, DUAL SERIAL INPUT, VOLTAGE OUTPUT, 12-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-09-14 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95667 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-
4、E133-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two prod
5、uct assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RH
6、A) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95667 01 M E A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.
7、2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator.
8、A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 MAX532A Dual serial input, voltage output, 12-bit multiplying digital-to-analog converter 02 MAX532B Dual serial input, voltage output,
9、 12-bit multiplying digital-to-analog converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant,
10、non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP
11、2-T16 16 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A
12、 5962-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VDDto DGND, AGNDA, AGNDB. -0.3 V, +17 V VSSto DGND, AGNDA, AGNDB+0.3 V, -17 V VREFA, VREFB. (VSS 0.3 V) to (VDD+ 0.3 V) AGNDA, AGNDB(DGND 0.3 V) to (VDD+ 0.3 V)
13、 VOUTA, VOUTB(VSS 0.3 V) to (VDD+ 0.3 V) RFBA, RFBB(VSS 0.3 V) to (VDD+ 0.3 V) SCLK, DIN, DOUT, LDAC , CS (DGND 0.3 V) to (VDD+ 0.3 V) DOUTsink current . 20 mA Junction temperature (TJ) +150C Storage temperature range -65C to +160C Lead temperature (soldering, 10 seconds) +300C Continuous power diss
14、ipation, TA= +70C (PD): Derate linearly 10.0 mW/C above +70C 800 mW Thermal resistance, junction-to-case (JC) . 50C/W Thermal resistance, junction-to-ambient (JA) 100C/W 1.4 Recommended operating conditions. Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Governmen
15、t specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION
16、MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Micro
17、circuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event
18、 of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may
19、 cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95667 DLA LAND AND MARITIME COLU
20、MBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) pl
21、an. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and phys
22、ical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal co
23、nnections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and s
24、hall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1
25、.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall st
26、ill be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in
27、 MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this
28、 drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an appr
29、oved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conform
30、ance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime -VA of
31、change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to
32、 review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number
33、80 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical per
34、formance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max STATIC PERFORMANCE 2/ Resolution N 1, 2, 3 All 12 Bits Relative accuracy INL 1, 2, 3 01 -0.5 +0.5 LSB 02 -1.0 +1.0 Differential nonlinearity DNL Guaranteed m
35、onotonic 1, 2, 3 All 1.0 LSB Zero code offset error VOE DAC latch loaded with all 0s 1 All 2.0 mV 2, 3 01 3.0 02 4.0 Gain error AE DAC latch loaded with all 1s 1 01 2.0 LSB 02 5.0 2, 3 01 4.0 02 7.0 REFERENCE INPUTS (VREFA, VREFB) VREFA, VREFBinput resistance RIN1, 2, 3 All 8 13 k VREFA, VREFBinput
36、resistance matching RMATCH1, 2, 3 All 3.0 % DIGITAL INPUTS (SCLK, DIN, LDAC , CS ) Input current IINVIN= 0 V or VDD1, 2, 3 All 1 A Input high voltage VIN1, 2, 3 All 2.4 V Input low voltage VIL1, 2, 3 All 0.8 V Input capacitance CIN3/ 4 All 8 pF DIGITAL OUTPUT (DOUT) 4/ Output voltage low VOLISINK= 5
37、 mA 1, 2, 3 All 0.4 V Output high leakage current ILKGVDOUT= 0 V to VDD1, 2, 3 All 10 A Output high capacitance COUT3/ 4 All 15 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596
38、2-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max ANALOG OUTPUTS (VOUTA
39、, VOUTB) Output voltage swing VOS1, 2, 3 All V POWER REQUIREMENTS Positive supply voltage VDD1, 2, 3 All 11.4 16.5 V Negative supply voltage VSS1, 2, 3 All -11.4 -16.5 V Power supply rejection ratio PSRRFull scale/VDD= 11.4 V to 16.5 V, VREF= -8.9 V, DAC latches loaded with all 1s 1,2,3 All 0.035 LS
40、B/% Full scale/VSS= -11.4 V to -16.5 V, VREF= 8.9 V, DAC latches loaded with all 1s 0.035 Positive supply current IDDOutput unloaded 1, 2, 3 All 10 mA Negative supply current ISSOutput unloaded 1, 2, 3 All 6 mA TIMING CHARACTERISTICS 5/, 6/ SCLKclock frequency fCLK9, 10, 11 All 6.25 MHz SCLKpulse wi
41、dth high tCH9, 10, 11 All 80 ns SCLKpulse width low tCL9, 10, 11 All 80 ns DIN to SCLKrise setup time tDS9, 10, 11 All 50 ns DIN to SCLKrise hold time tDH9, 10, 11 All 0 ns CS fall to SCLK rise setup time tCSS09, 10, 11 All 50 ns CS rise to SCLK rise setup time tCSS19, 10, 11 All 50 ns SCLKfall to C
42、S fall hold time tCSH09, 10, 11 All 5 ns SCLKrise to CS rise hold time tCSH19, 10, 11 All 80 ns CS pulse width high tCSW9, 10, 11 All 120 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING
43、SIZE A 5962-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max TIMING CHAR
44、ACTERISTICS continued 5/, 6/ SCLKfall to DOUTvalid tDOCL= 20 pF, RPULL-UP= 1 k to 5 V 7/ 9, 10, 11 All 0 200 ns CS fall to DOUTenable tDVCL= 20 pF, RPULL-UP= 1 k to 5 V 8/ 9, 10, 11 All 100 ns CS rise to DOUTdisable tTRCL= 20 pF, RPULL-UP= 1 k to 5 V 8/ 9, 10, 11 All 60 ns LDAC pulse width low tLDAC
45、9, 10, 11 All 60 ns CS rise to LDAC fall setup time tLDACS9, 10, 11 All 100 ns 1/ VDD= 11.4 V to 16.5 V, VSS= -11.4 V to -16.5 V, AGNDA= AGNDB= DGND= 0 V, VREFAand VREFB= +10 V, RL= 2 k, CL= 100 pF, VOUTconnected to RFB. 2/ Static performance tested at VDD= +15 V, VSS= -15 V. Performance over suppli
46、es guaranteed by PSR test. 3/ Guaranteed, if not tested, to the limits specified in table I. 4/ Open-drain output. 5/ All input signals are specified with tr= tf 5 ns. Logic input swing is 0 V to 5 V. 6/ See figure 2. 7/ Timing is for SCLKfall to DOUTfall to 0.8 V or for SCLKfall to DOUTrise to 2.4
47、V. Additional time must be added for any larger passive RC pull-up delay. 8/ DOUTenable: DOUTfalls to 4.5 V from 5.0 V. DOUTdisable: DOUTrises to 0.5 V from 0 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 596
48、2-95667 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 Device types 01 and 02 Case outline E Terminal number Terminal symbol 1 RFBA2 VREFA3 VOUTA4 AGNDA5 AGNDB6 VOUTB7 VREFB8 RFBB9 VSS10 DGND11 SCLK12 DOUT13 DIN14 CS 15 LDAC 16 VDDFIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95667 DLA LAND AND
