1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw. Update drawing to current requirements. drw 10-05-03 Charles F. Saffle REV SHET REV A A A A A SHEET 15 16 17 18 19 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Roo
2、ney DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Sandra Rooney APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 1394 HIGH-SPEED
3、SERIAL-BUS LINK-LAYER CONTROLLER MONOLITHIC SILICON DRAWING APPROVAL DATE 96-06-12 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-96770 SHEET 1 OF 19 DSCC FORM 2233 APR 97 5962-E224-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD M
4、ICROCIRCUIT DRAWING SIZE A 5962-96770 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (d
5、evice class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 96770 01 Q
6、 X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
7、are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as f
8、ollows: Device type Generic number Circuit function 01 TSB12C01AM 1394 high-speed serial-bus link-layer controller 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor
9、 self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and as follows: Outline le
10、tter Descriptive designator Terminals Package style X See figure 1 100 Quad flatpack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted wi
11、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96770 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/, 2/ Supply voltage range (VCC) -0.5 V dc to +6.0 V dc Input voltage range (VIN) -0.5 V d
12、c to VCC+ 0.5 V dc Output voltage range (VOUT) . -0.5 V dc to VCC+ 0.5 V dc Input clamp current (IIK) (VIVCC) . 20 mA Output clamp current (IOK) (VoVCC) . 20 mA Continuous power dissipation (case X) at 25C . 2885 mW 3/ Storage temperature range (TSTG) . -65C to +150C Thermal resistance, junction-to-
13、case (JC) . 11C/W Thermal resistance, junction-to-air (JA) . 60C/W Junction temperature (TJ). +175C Case temperature for 10 seconds: (TC) +260C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.75 V dc to +5.25 V dc Input voltage range (VIN) +0.0 V dc to VCCHigh level input voltage
14、 range (VIH) +2.0 V dc to VCCLow level input voltage range (VIL) . +0.0 V dc to +0.8 V Clock frequency, BCLK 33 MHz Operating free-air temperature range (TA) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and ha
15、ndbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT
16、 OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documen
17、ts are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
18、 text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may
19、degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ Above 25C, derate at a factor of 19.2 mw/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96770
20、DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device ma
21、nufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified here
22、in. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordanc
23、e with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specif
24、ied herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II.
25、The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufac
26、turer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
27、3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a ce
28、rtificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL
29、-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the re
30、quirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8
31、Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC
32、s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covere
33、d by this drawing shall be in microcircuit group number 38 (see MIL-PRF-38535, appendix A) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96770 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI
34、ON LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TA+125C 4.75 V VCC 5.25 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max High level output voltage VOHIOH= -4 mA 1,2,3 All VCC-0.8 V Low level output vo
35、ltage VOLIOL= 4 mA 1,2,3 All 0.5 V Positive-going input threshold voltage VIT+1,2,3 All 2 V Negative-going input threshold voltage VIT-1,2,3 All 0.8 V Low-level input current IILVIN= GND 1,2,3 All -1.0 A High-level input current IIHVIN= VCC1,2,3 All 1.0 A High impedance-state output current 1/ IOZVO
36、UT= VCCor GND 1,2,3 All 10 A Input capacitance CINVCC= 5.0 V, See 4.4.1b, TA= 25C 4 All 20.0 pF Bidirectional capacitance CI/O25.0Output capacitance COUT20.0 Host-Interface Timing Requirements 2/ Cycle time, BCLK tc1TA= 25C, See figure 4 9 All 30 ns Pulse duration, BCLK high tw1(H)TA= 25C, See figur
37、e 4 9 All 10 ns Pulse duration, BCLK low tw1(L)TA= 25C, See figure 4 9 All 10 ns Setup time, DATA (0:31) before BCLK tsu1TA= 25C, See figure 4 9 All 4 ns Hold time, DATA (0:31) after BCLK th1TA= 25C, See figure 4 9 All 2 ns Setup time, ADDR (0:7) before BCLK tsu2TA= 25C, See figure 4 9 All 12 ns Hol
38、d time, ADDR(0:7) after BCLK th2TA= 25C, See figure 4 9 All 2 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96770 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 R
39、EVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions -55C TA+125C 4.75 V VCC 5.25 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Setup time, CS before BCLK tsu3TA= 25C, See figure 4 9 All 12 ns
40、 Hold time, CS after BCLK th3TA= 25C, See figure 4 9 All 2 ns Setup time, WR before BCLK tsu4TA= 25C, See figure 4 9 All 12 ns Hold time, WR after BCLK th4TA= 25C, See figure 4 9 All 2 ns Host-Interface Switching Characteristics 2/ Delay time, BCLK to CA td1CL= 45 pF, See figure 4 9,10,11 All 4 16 n
41、s Delay time, BCLK to CA td2CL= 45 pF, See figure 4 9,10,11 All 4 16 ns Delay time, BCLK to DATA(0:31) valid td3CL= 45 pF, TA= 25C, See figure 4 9 All 4 24 ns Delay time, BCLK to DATA(0:31) invalid td4CL= 45 pF, TA= 25C, See figure 4 9 All 4 24 ns Phy-Interface Timing Requirements 2/ Cycle time, SCL
42、K tc2TA= 25C, See figure 4 9 All 20.24 20.45 ns Pulse duration, SCLK high tw2(H)TA= 25C, See figure 4 9 All 9 ns Pulse duration, SCLK low tw2(L)TA= 25C, See figure 4 9 All 9 ns Setup time, DATA(0:7) before SCLK tsu5TA= 25C, See figure 4 9 All 6 ns Hold time, DATA(0:7) after SCLK th5TA= 25C, See figu
43、re 4 9 All 0 ns Setup time, CTL(0:1) before SCLK tsu6TA= 25C, See figure 4 9 All 6 ns Hold time, CTL(0:1) after SCLK th6TA= 25C, See figure 4 9 All 0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC
44、UIT DRAWING SIZE A 5962-96770 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions -55C TA+125C 4.75 V VCC 5.25 V Group A subgroups Device type Limits Unit unless othe
45、rwise specified Min Max Phy-Interface Switching Characteristics 2/ Delay time, SCLK to D(0:7) valid td5CL= 45 pF, See figure 4, TA= 25C 9 All 3 14 ns Delay time, SCLK to D(0:7) td6CL= 45 pF, See figure 4, TA= 25C 9 All 3 14 ns Delay time, SCLK to D(0:7) invalid td7CL= 45 pF, See figure 4, TA= 25C 9
46、All 3 14 ns Delay time, SCLK to CTL(0:1) valid td8CL= 45 pF, See figure 4, TA= 25C 9 All 3 14 ns Delay time, SCLK to CTL(0:1) td9CL= 45 pF, See figure 4, TA= 25C 9 All 3 14 ns Delay time, SCLK to CTL(0:1) invalid td10CL= 45 pF, See figure 4, TA= 25C 9 All 3 14 ns Delay time, SCLK to LREQ td11CL= 45
47、pF, See figure 4, TA= 25C 9 All 3 14 ns Miscellaneous Timing Requirements 2/ Cycle time, CYCLEIN tc3TA= 25C, See figure 4 9 All 124.99 125.01 s Pulse duration, CYCLEIN high tw3(H)TA= 25C, See figure 4 9 All 62 s Pulse duration, CYCLEIN low tw3(L)TA= 25C, See figure 4 9 All 62 s Miscellaneous Signal
48、Switching Characteristics 2/ Delay time, SCLK to INT low td12TA= 25C, See figure 4 9 All 4 18 ns Delay time, SCLK to INT high td13TA= 25C, See figure 4 9 All 4 18 ns Delay time, SCLK to CYCLEOUT high td14TA= 25C, See figure 4 9 All 4 16 ns Delay time, SCLK to CYCLEOUT low td15TA= 25C, See figure 4 9 All 4 16 ns 1/ All outputs are in the high impedance state. 2/ All parameters are guaranteed but not tested at 25C except td1and td2. td1and td2are tested
