1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Corrected total dose irradiation to 1000 KRads(Si) (H level designator) in section 1.4. Update drawing to current requirements. Editorial changes throughout. tcr 09-10-01 Charles Saffle REV SHET REV A A A A A A SHEET 15 16 17 18 19 20 REV STATUS
2、REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218 - 3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTM
3、ENTS APPROVED BY Ray Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, RADIATION-HARDENED, 8K X 8-BIT MASK PROGRAMMABLE ROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-10-16 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-97544 SHEET 1 OF 20 DSCC FORM 2233
4、APR 97 5962-E470-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawi
5、ng documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation H
6、ardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 97544 01 Q Z C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3)
7、/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropria
8、te RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Input buffer type Access time 01 6664 8K X 8-bit radiation hardened mask PROM CMOS 45 ns 02 6664 8K X 8-bit radiati
9、on hardened mask PROM TTL 45 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class le
10、vel B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Z See figure 1 36 Flat p
11、ackage 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97544 DEF
12、ENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VDD) -0.5 V dc to +7.0 V dc Voltage on any pin with respect to ground . -0.5 V dc to VDD+0.5 V dc DC output current (IOUT) . 25 mA Maximum power
13、 dissipation (PD) . 2.5 W Lead temperature (soldering, 10 seconds maximum) +270C Thermal resistance, junction-to-case (JC): Case Z 2.0C/W Junction temperature (TJ). +175C Storage temperature range -65C to +150C Data retention 10 years (minimum) 1.4 Recommended operating conditions. Supply voltage (V
14、DD) +4.5 V dc to +5.5 V dc Ground voltage (VSS) . 0.0 V dc Case operating temperature range (TC) . -55C to +125C Radiation features: Total dose irradiation . 1000 KRads(Si) Single event phenomenon (SEP) effective linear energy threshold (LET) with no upsets . 120 MEV-cm2/mg Neutron irradiation 1 x 1
15、014neutrons/cm22/ 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) 100% 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
16、 part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE ST
17、ANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are availab
18、le online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may d
19、egrade performance and affect reliability. 2/ Guaranteed, but not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET
20、4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS
21、(ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken,
22、PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standa
23、rds and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and
24、the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shal
25、l be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in acco
26、rdance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendi
27、x A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table for unprogrammed devices shall be as specified o
28、n figure 3. 3.2.4 AC test circuit and timing characteristics. The ac test circuit and timing characteristics shall be as specified on figure 4. 3.2.5 Read cycle waveforms. The read cycle waveforms shall be as specified on figure 5. 3.3.6 Radiation exposure circuit. The radiation exposure circuit sha
29、ll be as specified on figure 6. 3.2.7 Pin function descripton. See 6.5. 3.2.8 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process changes which may affect dat
30、a retention. The methods and procedures may be vendor specific but shall guarantee data retention as specified in paragraph 1.3 over the full military temperature range. The vendors procedure shall be kept under document control and shall be made available upon request of the aquiring or preparing a
31、ctivity, along with test data. 3.3 AID requirements. All AIDs written against this SMD shall be sent to DSCC-VAS. The following items shall be provided to the device manufacturer by the customer as part of an AID. These items form a part of the manufacturers design database/database archive and shal
32、l be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. As such, these items will not appear in the AID in the traditional sense.
33、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.3.1 ROM mask definition. To generate a mask for
34、a ROM code, an ASCII file shall be submitted. The format for the code shall be as follows: a. Two fields, address followed by data in hexadecimal code, most significant bit to least significant bit (AH is most significant bit). b. Addresses need not be in order. c. Address and data fields must be se
35、parated by at least one space or a slash “/“. d. A semicolon “;“ may terminate the line, but is not required. e. No “end-of-file“ characters are required. f. Comments are preceded by the pound sign “#“. g. Comments may be on the same line AFTER address and data fields. h. Unused locations do not nee
36、d to be addressed, but MUST be specified as all zeroes or all ones. This can be done as a comment. 3.3.2 Fault coverage measurement of manufacturing logic tests. 3.3.3 Burn-in circuit. 3.3.4 Radiation exposure circuit. 3.3.5 Maximum device cross section for SEP. 3.3.6 Programmed devices. The truth t
37、able for final masked (programmed) devices shall be as specified in the altered item drawing. 3.4 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified, the electrical performance characteristics and postirradiation parameter limits are as specified
38、in table I and shall apply over the full case operating temperature range. 3.5 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.6 Marking. The part shall be marked with the P
39、IN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA desig
40、nator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.6.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“
41、as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.7 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requir
42、ements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approve
43、d source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.8 Certificate of conformance. A certificate of conformanc
44、e as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (se
45、e 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OH
46、IO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VDD 5.5 V unless otherwise specifiedGroup A subgroups Device type Limits Unit Min Max Output low voltage VOL1VDD= 4.5 V, IOL= 10 mA 1, 2, 3 All 0.4
47、 V M,D,P,L,R,F,G,H 1 1/ 2/ Output low voltage VOL2VDD= 4.5 V, IOL= 200A 1, 2, 3 All 0.15 V M,D,P,L,R,F,G,H 1 1/ 2/ Output high voltage VOH1VDD= 4.5 V, IOH= -200A 1, 2, 3 All VDD- 0.1 V M,D,P,L,R,F,G,H 1 1/ 2/ VOH2IOH= -5.0mA 1, 2, 3 All 4.2 M,D,P,L,R,F,G,H 1 1/ 2/ Input low voltage CMOS inputs VIL1V
48、DD= 4.5 V 1, 2, 3 01 0.3 x VDDV M,D,P,L,R,F,G,H 1 1/ 2/ Input low voltage TTL inputs VIL2VDD= 4.5 V 1, 2, 3 02 0.8 V M,D,P,L,R,F,G,H 1 1/ 2/ High-level input voltage CMOS inputs VIH1VDD= 5.5 V 1, 2, 3 01 0.7 x VDDV M,D,P,L,R,F,G,H 1 1/ 2/ High-level input voltage TTL inputs VIH2VDD= 5.5 V 1, 2, 3 02 2.2 V M,D,P,L,R,F,G,H 1 1/ 2/ Input leakage current IILK0 V VIN 5.5 V 1, 2, 3 All -5 5 A M,D,P,L,R,F,G,H 1 1/ 2/ 2/ Three-state output leakage current IOLK0 V VOUT 5.5 V 1, 2, 3 All -10 10 A Ou
