1、EIA JEBLS 72 W 323L1b00 0003050 8 W - . NOVEMBER i972 JEDEC ENGINEERING BULLETIN No.19 RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS JEDEC Solid State Products Engineering Council EIA JEB1 72 3234b00 0003051 T Published by ELECTRONIC INDUSTRIES ACSOCIATION Engineering Department 2001 Eye Stree
2、t, N.W. Washington, D.C. 20006 Printed in U.S.A. EIA JEBIIS 72 M 3234600 0003052 II JEDEC ENGINEERING BULLETIN NO. 19 Recommended Characterization of MOS Shift Registers Formulated by JEDEC Committee JC-40 on Digital Monolithic Integrated Circuits and approved by the JEDEC Solid State Products Counc
3、il November 1972 . EIA JEBLS 72 = 3234b00 0003053 3 RECOMMENDED CHARACTERIZATION OF MOS SHIFT WGISTERS SCOPE This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation. 1. ABSOLU
4、TE MAXIMUM ATINGS 1.1 Temperature 1.1.1 Storage Temperature Range, TSTG 1.1.2 Temperature Range Under Bias, TA (ambient) or TC (case) 12 Terminal Voltage and/or Current Maximum voltage and/or current limits at any one or all terminals referenced to a commonterminal shall be speci- fied for the speci
5、fied cambient or case) temperture range. 2. ELECTRICAL CHARACTERISTICS 2.1 Operating Conditions 2.1.1 Parametric Limits The following notation* for limits for logic levels, input parameters, output parameters, and supply voltage and current are preferred and defined as: “A“ For that value which is n
6、earest to positive “B“ for that value which is nearest to negative infinity infinity Examples showing the use of subscripts “A“ and “B“ are shown on the following page: J; International Electrotechnical Commission 47 (C .O .) 361. -1- ta, ! o- -1 EIA JEBLS 72 3234600 0003054 5 2.1.1.1 Voltage Levels
7、 “HA HB . ta, “LA VHA HB . “LA . LB . tw . I H I o .- Il L Il “HA - - “HB - V - .“LB “03 EIA JEBLS 72 W 3234600 0003055 7 W 2.1.1.2 Current Levels +a +Ca f . IHA IHB (Posi tive-current into a te.rmina1) , ILA . ILB E iL I L “ . *_ i -_ : IHA IHB. (Ne ga t i ve -c urre n t out of a terminal: ILA -. /
8、 ILB - 2.1.2 Power Supply Notation As noted in 2.1.1, the preferred limits of A and B should be used for the power supply voltages. should be used for power supply notation. For example: A double subscript P -MO S N-MOS c-MO s vw VGG vw vss VDD VDD VDD Mo s t Pos it ive Positive Intermediate .- Nega
9、tive vss Mo s t Negative VGG VUU vss Substrate Vuu or VSS VUU or VSS VUU or VDD NOTE: If the substrate has a separate bias, that voltage shall be called Vm. -3- I I EIA JEBLS 72 M 3234600 000305b 9 2.1.3 Clock or Control Notations The follwoing are recommended symbols for clock or control signal not
10、ation: Clock -Q Chip Enable - CE 2.2 Static Characteristics 2.2.1 Input - This includes all inputs such as data, clock, write/recirculate, read, and other controls. 2.1.1.1 Voltage - High level is the most positive value, low level is the most negative value. VIH - A and B limits VIL - A and B limit
11、s 2.2.1.2 Current III4 at VIHA IILB at VILB (Examples of terminology - clock input high level current - IIH 2.2.1.3 Protection - Input protective devices shall be specified as a minimum and maximum voltage, V(gR) I., at specif ied current. 2.2.2 Output - Separate measurements shall be included for t
12、he high impedance state of a three-state output. 2.2.2.1 Current - Use A or B limit as appropriate IOL at vou %L at VOLB QH at VOM IOH at VOHB 2.2.2.2 Resistance - Optional min. at IOL or VOL % max. at IOL or VOL min. at QH or VOH Ro max. at %H or VOH 2.2.3 Power Supply Current - Average value of po
13、wer supply current under worst case steady state conditions of voltage, frequency, and clock duty cycle. Iss IDD No tat ions correspond to supplies I&) . listed under 2.1.2 -4- t EIA JEBLS 72 3234b00 0003057 O _._ -e& 2.3 Dynamic Characteristics 2.3 1 Capacitance Ci - Input Capacitance Cd - Clock Ca
14、pacitance Co - Output Capacitance 2.3.2 Timing Diagrams at 250G - Examples given use recommended 10% and 90% points but 5(X points or voltage levels are voltage bounds on input and output wave forms and all percentages refer to these specified bounds. The dy- namic load should be depicted schematica
15、lly with values listed in a footnote to the output diagram. Transition“ is defined as the transition of the clock signal which triggers action. Its use is recommended where applicable and instructive. .acceptable. The timing diagrams should include the “Active 2.3.2.1 Data (and control, if applicabl
16、e) Set-up Time, tDS min., and Hold Time, tDH min. Clock . IH6 Active Transition t I EIA JEBLS 72 m 3234b00 0003058 2 m 203.202 I t Propagation Delay - High to Low Transition v Clock * : , VL, “OH Data Out _. 10% “OL Propagation Delay - Low to High Transition 2.3.2.3 H . : Clock . 10% v “OH Data Out 2,3.2 . 4. Clock Timing Requirements VIHg51 - 90kr Active Transition . IY Clock . “ILI Clock 2 V NOTE : tp is used tv is used for pulse width at 10% or 90% value, for pulse width at 50% value. Ref: JmEC Publication No. 77 -6-
