1、, U EIA JEPLLb 91 3234600 0078376 b Reproduced By GLOBAL ENGINEERING DOCUMENTS With Th8 Permission of EIA Under Royaity Agreement p JEDEC PUBLICATION CMOS Semicustom Desian Guidelines JEPI 16 NOVEMBER 1991 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT %- Obirind from W h, Imin, CA 92714 -
2、? (714) 261.1455 (800) 854-7179 : EIA JEPLLb 91 W 3234600 0078377 8 E _ f # NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC S
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6、ssume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC O
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9、the For information Publications OEce 2001 Pennsylvania Ave., N.W. Washington, D.C, 20006 (202)457-4963 - 1 EIA JEPLLb 91 = 3234600 0078377 L W - CONTENTS JEP116, 1. introduction C. .l 0 2. Planning a Semicustom Design , .3 .3 *4 2.1. Product Specification , 2.3. Partitioning , 2.2. Design Methodolo
10、gy. . .3 2.4. Simulation Approach. , ._ 5 -* 2.5. Tedng . .5 2.6. Packaging . . -. 5 3. Internal Logic Design Considerations , .7 I 3.1. CMOS Design Practices . .8 3.2. Design Performance . . . 12 3.3. Testability . . 19 3.4. Power Dissipation . . 21 l 4. External Design Interface Considerations . .
11、 25 i 4.1. I/O Interface Levels , . 25 4.2. Output Drive . . 25 4.3. Performance Considerations , . 28 . 28 4.4. Noise . 33 4.5. Power and Ground Pin Placement . 4.6, Power Dissipation Considerations . . 36 . 39 5. Simulation , 5.1, Purpose of Simulation . . 39 5.2. General Guidelines and Procedure
12、. . 39 . 41 . 41 - I l l 5.3. Functionality , 5.4. Performance . 5.5. Fault Simulation, . . 42 I l 6. Testing Considerations , . . . 45 6.1. Functional Testing . * 45 6.4. Board Level Testing , . 53 6.2. OC Parametric Testing . . 52 6.3. AC Parametric Testing . . 52 7. Packaging Considerations . . 5
13、5 7.1. Mechanical Considerations . . 55 7.2. Performance Considerations . . 55 7.3. Power Dissipation and Temperature. . 57 7.4. Board Assembly Considerations . . 59 8. Summary -63 9. Bibliography .6!5 i JEPI 16 Appendix A: Overview of Semicustom Packages . - _ - A.l Types of Packages - and the Trad
14、e-offs . . A.2 Through Hole Packages: DIPS . . A.4 Advances in Through Hole Packaging . A.5 Surface Mount Devices - General . A.6 Surface Mount Devices: Flatpacks . A.7 Surface Mount Devices: Leadless Chip Carriers (PQCC. and CQCC) A.8 Surface Mount Devices: Leaded Chip Carriers (PQCC and CQCC) A.9
15、Advances in Surface Mount Packages . A. 1 O Packaging for High Power Dissipation . A.11 Socketing Surface Mount Devices . A. 12 Noise Problems with Sockets . A.13 Surface Mount Packages for ASICs: What are the Tradeoffs . A.14 SMD Electrical and Thermal Characteristics . A.16 TAB Packaging. . A.17 P
16、ackage Selection Check List . A.3 Through Hole Packages: PGAs . , A.15 Packaging Problems and their Resolution . f. . 69 69 69 69 71 72 72 74 75 77 77 79 80 81 81 81 81 83 . 1 EIA JEPLLb - 71 W 3234600 007B38L T I - JEPI 16 Page 1 (From JEDEC Council Ballot JCB-90-36 formulated under the cognizance
17、of JC-44 on Semicustom ICs.) 1. INTRODUCTION The design f ASICcircuits is becoming a significant part of system or product design, yet many problems continue to exist in current design practice. The guidelines in this document provide an explanation of common ASIC design problems and concerns and wh
18、ere possible offer sdutions. ASIC circuits, which include standard cells, gate arrays, and cell-based circuits, differ prinkrily in the tech- nique used for placement of the cells and interconnect routing. The current mainstream of the industry is often assumed, with references to 5 voit power and l
19、ogic constructed with CMOS FETs. The guidelines assume CMOS technology and do not discuss those issues unique to other technologies such as ECL and Gallium Arsenide. There is no attempt to consider mixed mode or analog arrays. The information in these guidelines may be of some help in designing with
20、 other technologies, but that is not the purpose. The design of the circuit follows the same process, differing primarily in the complexity of the cells available for use in the circuit design (Figure 1 .i). Despite these variations, the design process for ASIC circuits follows an established patter
21、n common to ail vendors. The guidelines address issues of general concern to the ASIC circuit user as he proceeds with the design process. These guidelines are of primary interest to ASIC designers, but will also benefit ASIC vendors, users, and others involved in the evaluation and procurement of s
22、emicustom circuits. The guidelines include the design approach, issues in deciding how to do the circuit, the design and simulation, the /O interface, packaging, and testing. Although an attempt is made to be thorough in the coverage of these areas, some issues may have been overlooked and omitted.
23、The text is a consensus of design information gathered by members of the ASIC Standards (JC-44) committee of the Electronics industries Association. EIA JEPLLb 9% 3239b00 0078382 L E 1 a . DESIGN AND SPECIFICATION FNCnONALAND r TIMING SIMULATION l-l DESIGN VERIFICATION c CIRCUIT LAYOUT POST-LAYOUT S
24、IMULATION 1 1 TESTGENERATION I PROTOTYPE FABRICATiON I I PRODUCTION 1.1 Design flow for a Semicustom Circuit EIA JEPLLb 91 I 3234b00 0078383 3 = I. JEPI 16 Page 3 2. PLANNING A SEMICUSTOM DESIGN The variety of design approaches and CAD tds available provide the designer of ASIC circuits many choices
25、 which determine the outcome of the design. Some designs require special tods or design methods. In many cases the approach can affect the schedule and the difficulty of the design, Careful review of the design approach is required by the designer to anticipate problems and select the tools needed f
26、or success in the design. . In order to provide documentation and a visual overview of the device being developed, it is recommended that the initial schematic and subsequent modifications be captured, ie., developed with Computer Automated Design/Engineering (CAD/CAE) tools which are available from
27、 many vendors. This lnterconnection/relational data can be submitted for further analysis in the same or different environment. 2.1. Product Specification The most important document in the development of a product is the specification which defines the func- tion of the device and the interface req
28、uirements to a system. This document should specify the fdlowing features: 1. 2. 3. 4. 5. 6. 7. 8. 9. 1 o. operating voltages operating and storage temperatures maximum operating frequency . functional requirements . . testing features terminating impedancetinput and output output loading . referenc
29、e specifications for environmental testing reference specifications for reliability requirements packaging specification This specification should also define the reliability levels, and reference testing requirements (eiectrical and mechanical), and a qualified vendors list. A well conceived specif
30、ication will save substantial time in the development of a product since it will allow many groups within a company to review the design and prevent last minute interface and cost problems from arising. The packaging requirements are especially important. For example, specifying a 100 pin plastic fl
31、at pack is not an adequate description of the package. 100 pin plastic flat packs are available in both square and rectangular form factors. They are available in both metric and English lead pitches. Many companies will devgop a device without a specification of this detail. However, they will be u
32、suaily be susceptible to major delays in the development schedule without some formal description of the product and its impact on the manufacturing. 2.2 Design Methodology The design methodology is a description of the principles and flow to be used to develop a product for the company. It addresse
33、s the coordination levels required between different stages of product development. This Is particularly important when the end product will have a relatively long product life. Present and fu- ture techndogies by which the product will be produced must be considered. The partitioning of a design sh
34、ould consider the possible replacement on one or more modules with new devices which utilize higher speed technoiogies as they becomes available. The procedure or methoddogy should be defined to answer the following questions: l. Is design file portability required, and if required what Ml be the fo
35、rmat to obtain portaMM EIA JEPLLb 9L m 3234b00 0078384 5 m I ,I a * JEP116 Page 4 2. Will logic synthesis be used? . 3. 4. What Will be defined as the check points at which the design will be revlewed and by whom? Is multichip simulation required? If so, are there simulation models for devics with w
36、hich the chip under design must interface? 5. Is scan design required? 6. Is Built In Test (BIT) required? 2.3 Partitioning Partitioning a design into ASIC circuits is the most important decision after determining the function of the design. The method of partitioning will have a great impact on the
37、 cost and longevity of a system. Some of the considerations are: 1. 2, 3. How can the system be partition to have the least effect on the critical delay paths? How can the system be partitioned to effectively use the least expensive package? How can the system be partitioned to segregate modules whi
38、ch can be migrated for future upgrades, or can be used in multiple systems or products? When partitioning a system into ASICs, there are a number of criteria which guide the scalpel as to where the “incisions“ will be made, namely: Avoid partitions which “cut“ critical paths. It is desirable to prev
39、ent critical paths from spanning chip boundaries where possible unless access to these nodes is necessary to drive external components. D1 EI d I THE INl“TO VOIS FLOATS WHENEl=EZ=M=O. THIS IS NOT WOWED. iT IS NECESSAKYTO DESIGN LOGIC SUCH AS E3 = (El + E21. TO MAKE ONE OFTHE 3-STATE STATEMENIS TO BE
40、 ALWAYS CN. OR USE THIS CIRCUTT: DI T E2 E3 Figure 3.1 Avoiding Floating Buses *7 I EIA JEPLLb 91 W 3234600 0078390 O W JEPI 16 Page 10 Another floating node problem can occur due to insufficient noise margin on an input to a chip, where input noise causes the logic to switch. There are three possib
41、le solutions to the problem: Increase the noise margin by using a bdfer with a threshold further away from the signal levd. Vendors often offer both CMOS and TTL compatible input buffers which do have significantly dif- ferent thresholds. - 1. 2. Reduce the noise externally by filtering or biasing u
42、ntil the nuise magnitude is lower than the noise margin. If an input signal is slowly changing, a Schmitt trigger circuit can be used to sh the transition threshold and thus reduce the transition time between states. 3. 3.1.3. Unused Cell Outputs Some cells, such as a flip flop or counter, have more
43、 than one output, and at times not all outputs are needed. Leave these outputs open because: 1. The power dissipation will be minimized. 2. If the output signal feeds back into the cell, the speed will be reduced by loading the output. 3.1.4. Tying Cell Outputs Together In TTL designs, outputs of so
44、me TTL components can be tied together to produce AND or OR functions. CMOS logic has low impedance output, both for high and low output states, and should not be used such that a node is pulled simultaneously high and low. Excessive current flow from this condition can result in circuit failure. Wh
45、en a design is being converted from llL logic to a CMOS ASIC, and hac gate outputs tied together in wired AND and OR configurations, these logic functions must be added to the schematic and implemented as logic gates. 3.1.5. Fan-out Limitations Excessive loading of the output of a cell causes long r
46、ise and fall times, which increase current flow from Vdd to ground during the transitions of the signal. Excessive current could lead to a reliability problem where the transition time is very long. Also, the cells driven by the slow output are subject to noise propagation and spurious switching whe
47、n the input signal level is between the high and low states. The use of buffers or cells with a larger drive capability will help maintain good rise and fail times. Most ASIC vendors specify the maximum fan-out for each cell type to limit rise and fall times. Clocks used to drive edge triggered circ
48、uits are especially sensitive to slow rise and fall times, Special attention should be given to clock drive circuits. By designing with sufficient drive for good rise and fall times, problems with noise and marginal performance can be avokied. 3.1.6. Clocking, Setting, and Resetting Flip-flops and L
49、atches The design of latches and flip-flops for CMOS ASIC circuits is done in a number of ways. One way is to duplicate the edge triggered TTL version of the ceil with CMOS. Another popular CMOS technique is to use transmission gates driven by the clock to select either an input or feedback path. This latch circuit produces output similar to the edge triggered D latch in that a change In state occurs with the edge of the dock. The advantage of the transmission gate latches Is that fewer transistors are needed. A third but less popular method for making latches i
