JEDEC JEP121A-2006 Requirements for Microelectronic Screening and Test Optimization《微电子闪变和测试优化要求》.pdf

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1、JEDEC STANDARD Requirements for Microelectronic Screening and Test Optimization JEP121A (Revision of JEP121, April 1995, Reaffirmed September 20003) OCTOBER 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and ap

2、proved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability

3、and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard

4、to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC sta

5、ndards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an A

6、NSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-

7、7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2006 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or re

8、sell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be repro

9、duced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Public

10、ation No. 121A Page 1 REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION (From JEDEC Board Ballot, JCB-06-60, formulated under the cognizance of the JC-13.2 Subcommittee on Mircoelectronic Devices.) 1 Scope This document defines the methodology for the optimization (elimination, reduct

11、ion, or alternative approach) of the MIL-PRF-38535 screening and testing requirements for MIL-PRF-38535, Classes Q and V, Microcircuits. Inherent in this methodology is the application of “In-line Process Controls“ and “SPC“ techniques to the applicable manufacturing processes. This document include

12、s the process for initial approval and subsequent maintenance of the testing and screening optimizations. The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufactur

13、er in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. 2 Referenced documents 2.1 Military specifica

14、tions MIL-PRF-38535, Integrated Circuits (Microcircuits) Manufacturing, General Specification For 2.2 Military Standards MIL-STD-883 (Test Method Standard Microcircuits) 2.3 EIA Documents/publications ANSI/EIA Standard No. 557, Statistical Process Control Systems EIA-625 Requirements for Handling El

15、ectrostatic- Discharge-Sensitive (ESDS) Devices JEDEC publication No. 132, Process Characterization Guideline JEDEC Publication No. 121A Page 2 3 General Requirements 3.1 Test Optimization Foundation The manufacturer has to establish the foundation for “Test Optimization“ before implementing these o

16、ptimizations into the manufacturing and/or test flow. The manufacturing flow shall have an SPC system in place and an underlying philosophy that assures continuous improvement. Each critical operation relative to optimization of test shall have controls sufficient to ensure product meets the Technol

17、ogy Conformance Inspection (TCI) requirements of MIL-PRF-38535. The applicable Level I, II, and III quality characteristics controls defined herein shall be in place for the test to be eliminated. A facility granted approval for optimization of tests shall pursue efforts toward continuous improvemen

18、t. This assumes changes to the approved system and associated critical operations will occur. As changes to Level I, II and III quality characteristics control system are implemented, the manufacturer shall assure that sufficient evaluations have been performed to prevent the generation of defects t

19、hat would result in degradation in product performance at a test that has been optimized. The manufacturers control system shall be sensitive to detrimental trends or shifts in the process that may appear in the product. Changes in the Level I, II and III quality characteristics control system shall

20、 be communicated to the qualifying activity in accordance with the specified change notification requirements. This publication primarily focuses on the required controls to eliminate screens and/or tests. The manufacturer may use other “test optimization” approaches to detect potential quality and

21、reliability issues, such as; modify manufacturing flow to minimize handling and reduce risk of potential product damage, use in-process controls or tests for earlier detection, develop alternative sampling plans, or develop alternative test techniques to effectively identify and/or screen defective

22、product. These alternative approaches should consider the Level I, II, and III quality characteristics described herein, and understand the potential causes and detection of process quality or reliability defects as applicable in establishing the alternative test plans. 3.2 Statistical Process Contr

23、ol (SPC) System An SPC system must be fully implemented before test optimization is initiated. A comprehensive SPC system must first be developed in accordance with EIA Standard 557. JEDEC Publication 132 can be used as a guideline to assist the manufacturer in characterizing processes. 3.3 Quality

24、characteristics Once the SPC system is fully implemented, the manufacturer can start the optimization of screens and or tests. The first step in this process is the identification of the primary quality characteristics that are to be controlled. The “Quality Characteristics“ are those measurable pro

25、duct parameters identified and defined by the manufacturer as critical to the device operation or function. 3.3.1 Level I quality characteristics Level I quality characteristics are measurable by the customer on the end product. The relationship between Level I characteristics and the potential effe

26、ct on product performance varies widely for each product parameter. JEDEC Publication No. 121A Page 3 3.3 Quality characteristics (contd) 3.3.2 Level II quality characteristics Level II quality characteristics are process parameters that occur at the critical process node which relate to the output

27、Level I Quality Characteristics. 3.3.3 Level III quality characteristics Level III quality characteristics are those parameters controlled prior to the process. This includes material and environment parameters (e.g. gases, chemicals, D.I. water, humidity, etc.) affecting each critical process node.

28、 These parameters must be characterized with respect to the input/output relationships and interactions, and how they impact the Level I and II Quality Characteristics. The manufacturer must demonstrate how those parameters are under control. 3.3.3.1 Assuring quality of incoming materials The manufa

29、cturer must have an active control system in place to ensure the quality of incoming materials. This control may be accomplished by either requiring the supplier to have an SPC control system for the key parameter, or the manufacturers control system ensures the quality of received materials. 3.3.3.

30、2 Foreign Material Control System A foreign material control system shall be established which provides control, prevention, monitoring, sampling and reporting of foreign materials that may affect device performance. The plan must also involve corrective action when appropriate. 3.3.3.3 Electrostati

31、c Discharge/Electrical Overstress The manufacturer must have an ESD protection program in place in accordance with EIA625 to prevent potential damage to product. 3.4 Reinstitution of screens A plan must be in place to reinstitute the tests/screens if process controls or monitor tests indicate that c

32、ontrol is lost. A system must be in place for validating the integrity of the product when special cause signals occur. 3.5 Reliable product characteristics Manufacturers shall document a plan to demonstrate periodically that their manufacturing and quality systems ensure reliable performance in acc

33、ordance with MIL-PRF-38535 technology conformance inspections. The manufacturer shall define in their Quality Management (QM) Plan the frequency and sample plans for the performance of periodic re-validations of the TCI requirements. The frequency and sample size depend on whether; the screen and/or

34、 test had been eliminated, accomplished by an alternative method, or moved to a different point in the flow. JEDEC Publication No. 121A Page 4 3.6 Military specifications/standards changes Any changes to military specifications/standards that may impact any elimination or optimization of test condit

35、ions installed at any manufacturer shall be cause for the following: The responsibility lies with the manufacturer to perform an assessment to determine the impact of any specification changes on the test screen optimization program and the ability of the manufacturer to maintain test optimization.

36、This assessment for specification changes and any changes to the manufacturers test screen optimization program shall be provided to the qualifying activity. 3.7 Deviations from established procedures If product is exposed to additional or non-standard processing (examples include additional handlin

37、g resulting in ESD or foreign material exposure, or special tests) outside of established practices for the optimized Level I quality characteristic, then the manufacturer will apply appropriate actions to ensure product quality and/or reliability had not been compromised. 3.8 Test and field failure

38、s. When a test failure occurs during in-coming inspection, in-process monitor, end of line/TCI testing, or a confirmed field failure, and an associated screen or test has been optimized, then the following must be addressed. 1) The failure shall be analyzed to establish root cause. 2) If the failure

39、 analysis determines the cause of the failure is not related to the optimized test conditions, then corrective actions shall be taken in accordance with MIL-PRF-38535 requirements. 3) If the failure analysis determines the presence of the failure is associated with an optimized test, then the follow

40、ing actions must be taken. a) Product(s) for the optimized manufacturing flow shall not be processed using the affected optimization, but can use un-optimized processing until the following actions are successfully completed. b) Determine if the product quality and/or reliability is acceptable to th

41、e levels established for the implementation of test optimization. The defect rate can be determined by either using probability analysis to calculate the defect rate, or perform the standard TCI test to confirm product acceptance. c) If the levels are determined unacceptable then action must be take

42、n to identify affected product(s) for rescreen or retest, and notify affected customers to return product for retest. d) The affected screen or test must be modified to address the failure to achieve acceptable quality and/or reliability levels, and be submitted to the qualifying activity for test o

43、ptimization approval. If acceptable levels can not be achieved, then the standard screening or TCI test must be reinstated. e) The qualifying activity shall be notified and provided the information on the actions taken. f) The identified actions shall be documented and retained in accordance with re

44、cord retention procedure requirements. JEDEC Publication No. 121A Page 5 4 Streamlining matrix Table 1 compares the relationship/risk associated with a given process and the associated tests. In developing this data, the question was asked; “What is the relationship/risk between a process (e.g., sil

45、ver-glass die attach) and the 100% screen being considered (e.g., centrifuge)?“ It is based on this risk/relationship that all other tables were developed. For example, if there is a strong relationship between the process and the test, then all levels of process control (Level I, II, and III) are r

46、equired to satisfy the risk matrix. If there is a moderate relationship between the process and the test, then two levels of process control (Level I and II) are required to satisfy the risk matrix. If there is a slight relationship between the process and the test, then one level of process control

47、 (Level I) was required to satisfy the risk matrix. If there was no relationship between the two, then no level of process control was required. In some cases, the result of a process may be an incoming quality characteristic of another process. In those cases, the control of the incoming quality ch

48、aracteristic is picked up as a Level III control and called “DI“ (Direct Impact). For example, backside preparation is not considered as a Level I, II, or III quality characteristic for the elimination of centrifuge, but it is an incoming quality characteristic which must be considered for Level III

49、 of die attach. 4.1 Level I risk considerations (Annex A) This set of tables compares the Level I Quality Characteristics directly to the screen to be eliminated. If a check is present, this quality characteristic must be considered for the elimination of the screen. The process capability data must meet the characteristic defect rates and confidence levels specified below. The process capability study shall include evaluating lot to lot process variation. The number of lots and sample size depend on whether variables or attributes data are used. For example, the number of lots nee

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