1、 JEDEC PUBLICATION System Level ESD Part II: Implementation of Effective ESD Robust Designs JEP162 JANUARY 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level
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9、rth 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 162 -i- System Level ESD Part II: Implementation of Effective ESD Robust Designs Contents Page Introduction . iii I.1 Overview . iii I.2 Understan
10、ding Component to System ESD iv I.3 Communication and Strategy . v I.4 Implementation of Advanced Tools . v I.5 Impact from the Technology Roadmap . vi I.6 Conclusions . vi 1 Scope . 1 2 References . 1 3 Terms and Definitions . 6 4 Background and Outline 11 4.1 History of the Industry Council on ESD
11、 Target Levels 11 4.1 History of the Industry Council on ESD Target Levels (contd) .12 4.2 JEP162 (White Paper 3 Part II): Summary of Clauses/Annexes .12 4.2 JEP162 (White Paper 3 Part II): Summary of Clauses/Annexes (contd) .13 4.2 JEP162 (White Paper 3 Part II): Summary of Clauses/Annexes (contd)
12、.14 5 Overview of ESD Stressing and System Response 15 5.1 Presently Used Stress Tests for ESD .15 5.1 Presently Used Stress Tests for ESD (contd) .16 5.2 Definitions .16 5.2 Definitions (contd) .17 5.3 Coupling of ESD into Systems and Circuits .17 5.4 Troubleshooting to Determine the Cause of Failu
13、res 21 5.5 New Technologies for Determining Root Cause of Failures.21 5.6 Summary .24 6 State-of-the-Art ESD/EMI Co-design 24 Introduction 24 6.1 The Basics .25 6.2 Advanced System ESD Protection Methods .33 6.3 Comprehensive Co-Design Methodologies .38 6.4 Conclusion 39 7 Reference Methodologies fo
14、r IC/System Protection Co-Design 40 Introduction 40 7.1 Approaches Categories .42 7.2 Examples .52 8 Standard Model and Analytical Tool Needs To Support SEED 58 Introduction 58 8.1 Component Characterization and Model Requirements to Support SEED Category 1 .59 8.2 Component Characterization and Mod
15、el Requirements to Support SEED Category 2 .68 8.3 System Characterization and Model Requirements to Support SEED Category 3 .69 8.4 Conclusion 78 9 Summary and Conclusions.79 Introduction 79 9.1 Overview of ESD Stressing and System Response - Clause 5 79 9.2 State-of-the-Art ESD/EMI Co-Design - Cla
16、use 6 .79 9.3 Reference Methodologies for IC/System - Clause 7 .81 9.4 Standard Model and Analytical Tool Needs to Support SEED - Clause 8 82 9.5 Application Specific Information on System ESD Related Tests and Their Targets Annex A 82 9.6 Technology Roadmap and Direction Annex B 83 JEDEC Publicatio
17、n No. 162 -ii- 9.7 Outlook84 Annex A: Application Specific Information on System ESD related Tests and their Targets .85 Introduction 85 A.1 System Tests and Targets of Mobile Phones .85 A.2 System Tests and Targets of Automotive Electronic Components 87 A.3 System Tests and Targets of Computing Dev
18、ices 89 A.4 System Tests and Targets of Medical Electronic Components 90 A.5 System Tests and Targets of Avionic Components91 A.6 System Tests and Targets of Consumer Electronic Devices 92 A.7 Applicability of System-Efficient ESD Design (SEED) 93 Annex B: Technology Roadmap and Direction 95 Introdu
19、ction 95 B.1 Roadmap for ICs: Microprocessors .96 B.2 Roadmap for Automotive Applications .98 B.3 Roadmap for IC Package and Applications .99 B.4 Advances in Board and Assembly Technologies .101 B.5 Optical Interconnects .104 B.6 Polymer Applications .104 B.7 Future Compatibility to IEC Protection R
20、equirements 106 Annex C: Fast and Slow ESD Stress (High and Low Frequency Spectrum) 109 Discussion .109 C.1 Some Words on ESD Debugging .112 Annex D: Review of JEP161 (White Paper 3 Part I) 113 D.1 JEP161 Clause 4: Purpose and Introduction 113 D.2 JEP161 Clause 5: Test Methods and Their Field of App
21、lication .113 D.3 JEP161 Clause 6: Proven System Level Fails 115 D.4 JEP161 Clause 7: OEM System Level ESD Needs and Expectations .116 D.5 JEP161 Clause 8: Lack of Correlation between HBM/CDM and IEC 61000-4-2 .117 D.6 JEP161 Clause 9: Relationship between IC Protection Design and System Robustness
22、.118 D.7 JEP161 Clause 10: Summary, Conclusions and Outlook .120 Annex E: Frequently Asked Questions .121 Annex F: Revision History .127 JEDEC Publication No. 162 -iii- Foreword This document (JEP162) is the second of two Electrostatic Discharge (ESD) Industry Council white papers dealing with Syste
23、m Level ESD (Part I is JEP161). In JEP161, the misconceptions common in the understanding of system level ESD between supplier and original equipment manufacturer (OEM) were identified, and a novel ESD component / system co-design approach called system efficient ESD design (SEED) was described. The
24、 SEED approach is a comprehensive ESD design strategy for system interfaces to prevent hard (permanent) failures. In JEP162 we expand this comprehensive analysis of system ESD understanding to categorize all known system ESD failure types, and describe new detection techniques, models, and improveme
25、nts in design for system robustness. JEP162 also expands this SEED co-design approach to include additional hard / soft failure cases internal to the system. JEP162 begins with an overview of system ESD stress application methods and introduces new system diagnosis methods to detect weak ESD failure
26、 areas leading to hard or soft failures, and provides a “cost vs. performance vs. robustness” analysis of present-day state-of-the-art electromagnetic compatibility (EMC)/electromagnetic interference (EMI) design prevention methods that have been developed to prevent system level ESD failure. It fol
27、lows with an expansion of SEED failure classifications to cover a combination of hard (permanent) and/or soft (resettable) system failures and stresses which could cause these errors, and describes cases where the SEED co-design approach can be expanded to provide additional benefits to system ESD d
28、esign. System design simulation tools are described in the context of their potential improvements to simulating system level ESD stress and failure modes. Application-specific industry system ESD test methods are then described in the context of their ability to reveal hard and soft failure modes f
29、rom actual system deployment. Finally, a technology roadmap of the system design components is described, including IC technology and related circuit speeds, automotive electronics, packaging technology, system / board interconnect technology and ESD protection materials, illustrating continuing cha
30、llenges for system ESD design improvement. Introduction I.1 Overview JEP162, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. Thi
31、s objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI). This type of systematic approach is l
32、ong overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. In the first step, a method for categorizing the failure types has been introduced. An ad
33、vanced characterization and simulation approach is discussed through examples. However, a full design flow cannot be established without a common effort across the electronic industry involving IC suppliers, suppliers of discrete protection components and original equipment manufacturers (OEMs) as w
34、ell as tool vendors. This paper identifies existing tools with both simulations and scanning techniques that are applicable for this purpose and calls out fields for further development. JEDEC Publication No. 162 -iv- I.1 Overview (contd) Equally important is the notion that efficient system ESD des
35、ign can ideally be achieved by improved communication between the IC supplier, the OEM and the system builder. As technologies advance even further, and as systems become more complex under various applications, this shared responsibility is expected to gradually shift more towards system design exp
36、ertise. I.2 Understanding Component to System ESD Towards achieving the goals mentioned above, it is first important to decouple the component ESD requirements from system level ESD design. JEP155 and JEP157 established that component electrostatic discharge (ESD) levels can be safely reduced to pra
37、ctical levels with basic ESD control methods that are mandatory in every production area. We have also established that these ESD target levels enable fabrication of integrated circuits (ICs) with on-time delivery (in billions of units) for electronic systems in consumer applications with high circu
38、it performance. The general perception has been that component ESD (for example, human body model (HBM) is a prerequisite for good system level ESD robustness. But this misconception once again needs to be clarified, as shown below in Figure 1, system level ESD and component ESD are not correlated w
39、ith each other. Figure 1 Comparison of IC level and system level ESD failure threshold of various systems (A-J) showing that HBM protection is not related to System level ESD robustness In fact, at the system level, ESD robustness is a much more complex issue requiring a deeper understanding to addr
40、ess the ESD protection requirements for electronic systems such as laptops, cell phones, printers and home computers. These system complexities come about as a result of protecting the external interfaces, such as a universal serial bus (USB), to the outside world. Such systems, after encountering t
41、he more severe ESD pulses defined by the IEC standard, can lead to hard or soft failures. As introduced in JEP161, the basic version of system-efficient ESD design (SEED) addresses hard failures related to IC pins with a direct external interface, soft failures, which are more frequently reported, a
42、re challenging to understand and overcome. In this latter case, addressing soft failures requires an extension of the SEED approach to other failure mechanisms that include latch-up and EMI effects. In this document, the steps to categorize the different failure mechanisms, and the appropriate chara
43、cterization and simulation methodologies, are identified through various forms of Advanced SEED. JEDEC Publication No. 162 -v- I.3 Communication and Strategy This white paper documents a rigorous approach to describing the challenges related to all categories of system level ESD failures that can ar
44、ise from energy injection due to the IEC contact pulse stress, as well as from electromagnetic compatibility (EMC) and EMI effects. To classify these fails and to provide a common terminology, three categories of fails have been introduced: - SEED Category 1 (physical damage due to pulse energy) - S
45、EED Category 2 (damage or interference of function due to transient latch-up) - SEED Category 3 (interference of function by noise or bursts on supply net and signal lines) Understanding these different categories of failures is an important part of addressing the appropriate solutions. Thus, one ma
46、in objective is to close the existing communication gap between OEMs and IC providers by involving the expertise of both OEMs and system design experts. As a result, the completion of this second phase of White Paper 3 required the participation and contributions from world class experts on the art
47、of system level ESD phenomena and protection techniques. One of the challenges which remains elusive is the trade-off between cost, performance, robustness, and time-to-market. This white paper also addresses these issues, bringing forth a dialogue between the IC supplier, customer, and the system d
48、esigner. I.4 Implementation of Advanced Tools JEP162 specifically covers in detail an overview of system ESD stress application methods, system diagnostic techniques to detect hard or soft failures, and the application of tools for susceptibility scanning. For example, as illustrated in Figure 2, th
49、ese types of advanced tools can be used to differentiate the characteristics of products and enable proper system protection methodology. Figure 2 Susceptibility scanning using pulse techniques on Product A (left) and Product B (right) (Courtesy of Amber Precision Instruments) Along the lines of communication and interaction, IC suppliers and system designers can share their knowledge of tools and their applications. For example, suppliers would provide a single definition, high quality model of their input/output (IO). Then OEMs would use analytical tools to integrate
