1、JEDECSTANDARDRF BIASED LIFE (RFBL) TEST METHODJESD226 JANUARY 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the
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9、2201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 226 -i- RF BIASED LIFE (RFBL) TEST METHOD Contents PageForeword ii Introduction ii 1 Scope 1 2 Applicable documents 1 3 Apparatus 2 3.1 Circuitry 2 3.2 Device mounting 2 3.3 Power supplies and sig
10、nal sources 2 3.4 Environmental chamber 2 4 Definitions 3 4.1 Maximum operating voltage 3 4.2 Absolute maximum rated voltage 3 4.3 Absolute maximum rated junction temperature 3 4.4 Absolute maximum rated RF input power 3 5 Procedure 3 5.1 Stress duration 3 5.2 Acceleration Factor 4 5.3 Stress condit
11、ions 5 5.3.1 Ambient temperature 5 5.3.2 Operating DC voltage 6 5.3.3 Mode bias or functional dynamic bias 6 5.3.4 RF Biasing Configurations 7 5.3.4.1 Switching stress bias 7 5.3.4.2 RF stress bias 8 5.3.4.3 Modulated stress bias 8 5.3.5 Loading and matching 9 6 Cool-down 9 7 Samples 9 8 Measurement
12、s 10 8.1 Stress pauses 10 9 Failure criteria 10 10 Summary 11 JEDEC Standard No. 226 -ii- Foreword A unique application of semiconductor integrated circuits is within a module. Modules are sometimes referred to as a system-in-package (SIP) or hybrid. For the purpose of this document, we define a mod
13、ule as an assembly that integrates multiple semiconductor die within one package. Such a module is not restricted to semiconductors it can also contain passive devices that include components such as resistors, capacitors, inductors, filters, and couplers that are either built-in to the substrate or
14、 added as Surface Mount Devices. Another unique aspect of Laminate-based Power Amplifier Module (PAM) is the application of Compound Semiconductors. To further refine the classification of modules, we have specifically selected amplification to be the core function. But amplification is not necessar
15、ily the only function. Switching, power control, power detection, signal reception, filtering, and ESD suppression may be other functions performed within a module. Additionally, many of the functions may be employed over various frequencies and at various output power levels such that these functio
16、ns are arranged in a parallel fashion within the module. A typical module application is a Power Amplifier Module (PAM) used at or near the “front-end” of a cellular phone or mobile device. PAMs are an enabling component of cell phones that transmit signals with high efficiency, linearity, and relia
17、bility in a manner that is yet unmatched by monolithic devices. A typical PAM consists of a substrate, which may be a leadframe material, but is more commonly a ceramic or laminate multi-layer base. Upon the base, the aforementioned die and components are mounted, and all components are encapsulated
18、, using packaging materials, such as an epoxy, most commonly formed by a transfer mold process. Hermetic versions of PAMs utilize ceramic substrates and lids or caps that seal the various components within. Even though similar types of modules have been utilized for semiconductors in the past, the u
19、se of Compound Semiconductors, with a laminate substrate, for relatively high power dissipation wireless application at radio frequencies (RF) is seemingly unique. IntroductionThis standard is intended to address one of the unique operational regimes of a PAM: RF bias. DC bias and RF bias are differ
20、ent in many respects. One reference provided evidence that the thermal impact of RF Vs. DC was clearly evident. Specific comparisons between DC bias and RF bias are summarized by the following publication: 1 Y. Qu, P. Scott, L. Marchut, it is frequently specified by device manufacturers for a specif
21、ic device and/or technology. 5 Procedure The sample devices shall be subjected to the specified or selected stress conditions for the time and temperature required. It is desirable to perform RF stressing on the entire module. However, if the fully assembled module cannot be stressed, then RF lifete
22、sting of the individual subcomponents can be considered. If subcomponents are RF stressed, then measures must be taken to ensure the subassemblies represent the finished product as closely as possible. For example, the same thermal resistance, same junction temperature, and other similar conditions
23、must be applied. 5.1 Stress duration The bias life duration is intended to meet or exceed an equivalent field lifetime under use conditions. The duration is established based on the acceleration of the stress (see each specific failure mechanism - JEP122 for example). The stress duration is determin
24、ed by the specified qualification requirements (example, JESD 47) or the applicable procurement document. Interim measurements may be performed as necessary per restrictions in clause 7. JEDEC Standard No. 226 Page 4 5.1 Stress duration (contd) Without specific guidelines for a product, family, or t
25、echnology expectation, the minimum duration would be 500 hours, and the default duration would be 1,000 hours. The combination of stress conditions and duration should be chosen so that the RFBL test represents an accelerated version of the expected product lifetime. For example if the expected prod
26、uct lifetime is 5 years then the stress conditions should be chosen so that the minimum duration is determined by the following equation: Test Duration = (5 years) x (365.25 days/year) x (24 hours/day) = 43,830 hours (hours) AF Here the Acceleration Factor (AF) is the acceleration factor as discusse
27、d in 5.2. 5.2 Acceleration factor Many of the parameters used for biasing the device during the RFBL test can be used to stress the device beyond its normal use condition and contribute to the acceleration factor of the test. Common parameters used for PA modules include ambient temperature, current
28、, voltage and duty cycle. These factors should be chosen to be small enough to avoid device wear out during the duration of the test or inducing failure modes or mechanisms not expected during normal device operation. Each of these factors is discussed in more detail in the sections which follow. In
29、 this case the acceleration factor (AF) is given as: UseStressStressUseaNUseStressDutyCycleDutyCycleTTkEIIAFg184g184g185g183g168g168g169g167g184g185g183g168g169g167g184g184g185g183g168g168g169g167=11exp N is the Blacks Law factor for current acceleration, typically between 1 and 3. T is the junction
30、 temperature in Kelvin with contributions due both to ambient temperature and dissipated power. k is Boltzmanns constant. Eais the activation energy for extrinsic or random failures. If the activation energy is not known a nominal value of 0.7 eV is suggested for easy comparison purposes with other
31、results. The applied voltage is not included in the equation above, both voltage and current contribute to the junction temperature by increasing the dissipated power. Other acceleration models may be used if they are shown to accurately represent the technology used and expected application conditi
32、ons for the product under test. JEDEC Standard No. 226 Page 5 5.3 Stress conditions The stress condition shall be applied continuously (except during interim measurement periods). The time spent elevating the chamber to accelerated conditions, reducing chamber conditions to room ambient, and conduct
33、ing the interim measurements shall not be considered a portion of the total specified test duration. 5.3.1 Ambient temperature Unless otherwise specified, the ambient temperature and bias for high temperature stress shall be adjusted to result in a minimum hot spot temperature of the devices under s
34、tress high enough so that the accelerating condition requirement in section 5.2 is met but below any temperature where a failure mechanism not expected during normal use conditions becomes activated. One particular concern for overmolded modules is the glass transition temperature of the mold compou
35、nd. As a minimum requirement, chamber temperature must be set and recorded during stressing. If set or measured, package temperature, die temperature, and/or hotspot temperatures are beneficial and should be recorded for each sample or location. Estimates of the relationships of hot spot temperature
36、s to any other empirical temperatures should be recorded and included as part of the degradation analysis. ModuleChamberHeaterRF Input(s)Mode or Functional BiasRF Output(s)DC BiasPower SuppliesHighTemperatureChamber+-+Switching/PulseRFModulatedModulatedRFSwitching/PulseLoading this voltage must not
37、exceed the absolute maximum rated voltage for the device, including guard-banding, and must be agreed upon by the device manufacturer. 5.3.3 Mode bias or functional dynamic bias Unless otherwise specified, the Module is expected to exercise all of the operational modes anticipated in normal use. For
38、 example, all bands and all power levels should be cycled during the life test using dynamic or pulsed signals on the Module. Periodicity of the mode switching should approach the dynamics of operational expectations, if possible. If all of the operational modes cannot be induced and stimulated, the
39、n preference to the highest stress mode should be selected. Highest stress is to be determined by using the following priorities: 1) highest power dissipation, then 2) the highest voltage, then 3) the maximum number of internal nodes available to RF stimulus (see 5.3.4). Care must be taken not to ex
40、ceed maximum voltage fields, current densities, power dissipation, or induce prohibited truth table logic conditions. Testing all non-amplified RF pathways is desirable but not always possible. Stressing all switch legs may not be realistic, so representative pathways may have to be selected. An ass
41、umption is that stress will be maintained for 1,000 hour duration, so any switching of circuitry will result in less overall stress time for each section that is sharing signals. 5.3.4 RF biasing configurations Biasing configurations involving the signal path through the PAM may be: 1) switching str
42、ess (dynamic or pulsed), 2) operating stress (Radio Frequency), or 3) modulated stress (RF and duty cycle combination). Rated Duty Cycle should be demonstrated if possible. Modulation scheme should also be considered. It may not be possible to reproduce exact duty cycle/ modulation schemes in RFBL i
43、f not, then appropriate measures should be taken to ensure maximum junction/channel temperature is reproduced. Depending upon the biasing configuration, supply and mode bias input voltages may be grounded or raised to a maximum potential chosen to ensure a stressing temperature not higher than the m
44、aximum-rated junction temperature. Device outputs may be unloaded or loaded, to achieve the specified output power level. If a device has a thermal shutdown feature it shall not be biased in a manner that could cause the device to go into thermal shutdown. If dynamic bias is not applied to the signa
45、l path, then HTOL should be used instead of RFBL. JEDEC Standard No. 226 Page 7 5.3 Stress conditions (contd) 5.3.4 RF biasing configurations (contd) The goal for RF bias is use the maximum possible level expected for sustained operation. Care is necessary in applying an RF bias level when the ambie
46、nt temperature is raised above datasheet conditions (e.g., 125 C). If the RF drive level is set prior to raising the ambient temperature, then the RF drive may impact the circuit differently at the high temperature of the life test. Therefore, the RF level should be set according to best known pract
47、ices for the highest stress conditions and then carefully monitored as the temperature is elevated up to levels when oven stabilization is achieved during RFBL. With the primary goal to duplicate die temperature at worst case datasheet conditions, the shifting of RF power levels away (lower) from th
48、eir maximum settings may be necessary to elevate the oven temperature to the maximum for the duration of the RFBL stress. 5.3.4.1 Switching stress bias The Switching stress bias is defined as a pseudo RF condition. If actual RF signals cannot be applied, then low frequency or “digital” signals or pu
49、lsed signals may be substituted which exercise the signal path. The intent is to exercise the major power handling junctions of the device samples. The devices may be operated in either an alternating or a pulsed forward bias mode. Switched operation is used to stress the devices at, or near, maximum-rated current levels. The particular bias conditions should be determined to bias the maximum number of the solid state junctions in the device. Typically, several input parameters may be adjusted to control internal power dissipation.
