1、JEDEC STANDARD NAND Flash Interface Interoperability JESD230C (Revision of JESD230B, July 2014 OCTOBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and
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9、10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 230C Page 1 NAND FLASH INTERFACE INTEROPERABILITY (From JEDEC Board Ballot JCB-16-34, formulated under the cognizance of the JC-42.4 Subcommittee on Nonv
10、olatile Memory Devices.) 1 Scope This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support
11、 Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. 2 Terms, definitions, abbreviations and conventions 2.1 Terms and definitions address: A character or group of characters that identifies a register, a particula
12、r part of storage, or some other data source or destination. (Ref. ANSI X3.172 and JESD88.) NOTE 1 In a nonvolatile memory array, the address consists of characters, typically hexadecimal, to identify the row and column location of the memory cell(s). NOTE 2 For NAND nonvolatile memory devices, the
13、row address is for a page, block, or logical unit number (LUN); the column address is for the byte or word within a page. NOTE 3 The least significant bit of the column address is zero for the source synchronous data interface. asynchronous: Describing operation in which the timing is not controlled
14、 by a clock. NOTE For a NAND nonvolatile memory, asynchronous also means that data is latched with the WE_n signal for the write operation and the RE_n signal for the read operation. block: A continuous range of memory addresses. (Ref. IEC 748-2 and JESD88.) NOTE 1 The number of addresses included i
15、n the range is frequently equal to 2n, where n is the number of bits in the address. NOTE 2 For nonvolatile memories, a block consists of multiple pages and is the smallest addressable memory segment within a memory device for the erase operation. column: In a nonvolatile memory array, a series of m
16、emory cells whose sources and/or drains are connected via a bit line. NOTE 1 Depending on the nonvolatile memory array, the bit line is accessed via the column select transistor, the column address decoder, or other decoding scheme. NOTE 2 In nonvolatile memory device, a column decoder accesses a bi
17、t (x1), byte (x8), word (x16), or Dword (x32) either individually or within a page. NOTE 3 In a typical schematic of a memory array, the column is in the vertical direction. JEDEC Standard No. 230C Page 2 2.1 Terms and definitions (contd) Dword (x32): A sequence of 32 bits that is stored, addressed,
18、 transmitted, and operated on as a unit within a computing system. NOTE 1 A Dword may be represented as 32 bits, as two adjacent words, or as four adjacent bytes. When shown as bits, the least significant bit is bit 0 and the most significant bit is bit 31; the most significant bit is shown on the l
19、eft. When shown as words, the least significant word (lower) is word 0 and the most significant (upper) word is word 1. When shown as bytes, the least significant byte is byte 0 and the most significant byte is byte 3. NOTE 2 See Figure 1 for a description of the relationship between bytes, words, a
20、nd Dwords. latching edge: The rising or falling edge of a waveform that initiates a latch operation. NOTE 1 For a NAND nonvolatile memory the latching edge is the edge of the CK or DQS signal on which the contents of the data bus are latched for the source synchronous data interface. NOTE 2 For a NA
21、ND nonvolatile data cycles, the latching edge is both the rising and falling edges of the DQS signal. NOTE 3 For a NAND nonvolatile command and address cycles, the latching edge for the source synchronous interface is the rising edge of the CK signal. NAND defect area: A designated location within t
22、he NAND memory where factory defects are identified by the manufacturer. NOTE 1 The location is a portion of either the first page and/or the last page of the factory-marked defect block, this defect area in each page is defined as (# of data bytes) to (# of data bytes + # of spare bytes -1). NOTE 2
23、 For an 8-bit data access NAND memory device, the manufacturer sets the first byte in the defect area of the first or last page of the defect block to a value of 00h. NOTE 3 For a 16-bit data access NAND memory device, the manufacturer sets the first word in the defect area of the first or last page
24、 of the defect block to a value of 0000h. NAND nonvolatile memory device: The packaged NAND nonvolatile memory unit containing one or more NAND targets. NOTE This is referred to as “device“ in this standard. NAND row address: An address referencing the LUN, block, and page to be accessed. NOTE 1 The
25、 page address uses the least significant row address bits. NOTE 2 The block address uses the middle row address bits. NOTE 3 The LUN address uses the most significant row address bits. page: The smallest nonvolatile memory array segment, within a device, that can be addressed for read or program ope
26、rations. page register: A register used to transfer data from a page in the memory array for a read operation or to transfer data to a page in the memory array for a program operation. read request (for a nonvolatile memory): A data output cycle request from the host that results in a data transfer
27、from the device to the host. source synchronous (for a nonvolatile memory): Describing an operation in which the strobe signal (DQS) is transmitted with the data to indicate when the data should be latched. NOTE The strobe signal (DQS) is similar in concept to an additional data bus bit. JEDEC Stand
28、ard No. 230C Page 3 2.1 Terms and definitions (contd) status register (SRx): A register within a particular LUN containing status information about that LUN. NOTE SRx refers to bit “x“ within the status register. target: A nonvolatile memory component with a unique chip enable (CE_n) select pin. wor
29、d (x16): A sequence of 16 bits that is stored, addressed, transmitted, and operated on as a unit within a computing system. NOTE 1 A word may be represented as 16 bits or as two adjacent bytes. When shown as bits, the least significant bit is bit 0 and the most significant bit is bit 15; the most si
30、gnificant bit is shown on the left. When shown as bytes, the least significant byte (lower) is byte 0 and the most significant byte is byte 2. NOTE 2 See Figure 1 for a description of the relationship between bytes, words, and Dwords. 2.2 Abbreviations DDR: Abbreviation for “double data rate“. LUN (
31、logical unit number): The minimum memory array size that can independently execute commands and report status. N/A: Abbreviation for “not applicable“. Fields marked as “na“ are not used. O/M: Abbreviation for Optional/Mandatory requirement. When the entry is set to “M“, the item is mandatory. When t
32、he entry is set to “O“, the item is optional. 2.3 Conventions 2.3.1 Active-low signals While the preferred method for indicating a signal that is active when low is to use the over-bar as in CE, the difficulty in producing this format has resulted in several alternatives meant to be equivalents. The
33、se are the use of a CE reverse solidus ( ) or the trailing underscore ( _ ) following the signal name as in CE and CE_. In this publication “_n“ is used to indicate an active low signal (i.e., an inverted logic sense). 2.3.2 Signal names The names of abbreviations, initials, and acronyms used as sig
34、nal names are in all uppercase (e.g., CE_n). Fields containing only one bit are usually referred to as the “name bit“ instead of the “name field“. Numerical fields are unsigned unless otherwise indicated. 2.3.3 Precedence in case of conflict If there is a conflict between text, figures, state machin
35、es, timing diagrams, and/or tables, the precedence shall be state machine, timing diagrams, tables, figures, and text. JEDEC Standard No. 230C Page 4 2.4 Keywords Several keywords are used to differentiate between different levels of requirements or suggestions. mandatory: A keyword indicating items
36、 to be implemented as defined by a standard. Users are required to implement all such mandatory requirements to ensure interoperability with other products that conform to the standard. may: A keyword that indicates flexibility of choice between stated alternatives or possibly nothing with no implie
37、d preference. optional: A keyword that describes features that are not required by the specification. However, if any optional feature defined by the specification is implemented, that feature shall be implemented in the way defined by the specification. reserved: A keyword indicating reserved bits,
38、 bytes, words, fields, and opcode values that are set-aside for future standardization. Their use and interpretation may be specified by future extensions to this or other specifications. A reserved bit, byte, word, or field may be cleared to zero or in accordance with a future extension to this pub
39、lication. A host should not read/use reserved information. shall: A keyword indicating a mandatory requirement. should: A keyword indicating flexibility of choice with a strongly preferred alternative. This is equivalent to the phrase “it is recommended“. 2.5 Byte, Word and Dword Relationships Figur
40、e 1 illustrates the relationship between bytes, words and Dwords 7 6 5 4 3 2 1 0 byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 word byte 1 byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Dword word 1 word 0 byte 3 byte 2 byte 1 byte 0 Figure 1 Byte, word and
41、 Dword relationships JEDEC Standard No. 230C Page 5 2.6 Pin description Table 1 Pin description Name Input/ Output Description IO0 IO7( IO15) DQ0 DQ7 DQ0_x DQ7_x I/O DATA INPUTS/OUTPUTS These signals are used to input command, address and data, and to output data during read operations. The signals
42、float to high-z when the chip is deselected or when the outputs are disabled. IO0 IO15 are used in a 16-bit wide target configuration. With multi channel support, IO0_0IO7_0 and IO0_1IO7_1 are used for IOs of channel 0 and IOs of channel 1 respectively. Also known as DQ0DQ7 for Toggle DDR and Synchr
43、onous DDR. The number after the underscore represents the channel. For example, DQ0_0 indicates DQ0 of channel-0 and DQ0_1 does DQ0 of channel-1. CLE_x I COMMAND LATCH ENABLE The CLE_x signal is one of the signals used by the host to indicate the type of bus cycle (command, address, data). ALE_x I A
44、DDRESS LATCH ENABLE The ALE_x signal is one of the signals used by the host to indicate the type of bus cycle (command, address, data). CEx_x_n I CHIP ENABLE The CEx_x_n input is the target selection control. When CEx_x_n is high and the target is in the ready state, the target goes into a low-power
45、 standby state. When CEx_x_n is low, the target is selected. The number after the first underscore represents the channel. For example, CE0_0_n indicates CE0_n of channel-0 and CE0_1_n does CE0_n of channel- 1. WE_x_n I WRITE ENABLE The WE_x_n input controls writes to the I/O port. For Asynchronous
46、SDR Data, commands, addresses are latched on the rising edge of the WE_x_n pulse. For Toggle DDR commands, addresses are latched on the rising edge of the WE_x_n pulse. R/B_x_n O READY/BUSY OUTPUT The R/B_x_n output indicates the status of the target operation. When low, it indicates that one or mor
47、e operations are in progress and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. RE_x_n (RE_x_t) I READ ENABLE The RE_x_n input is the serial data-out control. For Asynchronous SDR Data
48、 is valid tREA after the falling edge and for Toggle DDR Data is valid after the falling edge 7uA1 ILOpu Pull-Up Output leakage current: DQ are disabled: VOUT=0V; ODT disabled 7uA1 NOTE 1 Absolute leakage value per DQ pin per NAND die. The following signals are required to meet output leakage (DQ7:0
49、, DQS_t, DQS_c, RE_t, RE_c) JEDEC Standard No. 230C Page 11 4 Package and Addressing 4.1 BGA-63 (Single x8 / x16 BGA) Figure 4 defines the ball assignments for devices using NAND Single x8 / x16 BGA packaging with 8-bit data access for the asynchronous SDR data interface. Figure 5 defines the ball assignments for devices using NAND Single x8 / x16 BGA packaging with 8-bit data access for the synchronous DDR data interface. Figure 6 defines the ball assignments for devices using NAND Single x8 / x16 BGA packaging with 16-bit data access for the asynchronous SDR dat
