1、 JEDEC STANDARD Byte Addressable Energy Backed Interface JESD245A (Revision of JESD245, December 2015) SEPTEMBER 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors
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9、103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 245A -i- BYTE ADDRESSABLE ENERGY BACKED INTERFACE, VERSION 2.0 DRAFT 3 Contents Page Foreword ii Introduction ii 1 Scope 1 2 Normative referenc
10、es 1 3 Terms and definitions 1 4 Introduction 5 5 I2C 6 6 Serial Presence Detect 12 7 Features 13 8 Register Map 23 9 Host Operation Workflows 95 Annex A Annex B Differences between revisions Figures 1 NVDIMM overview 6 2 Legend for I2C operations 7 3 I2C Read Byte 8 4 I2C Write Byte 8 5 I2C Block R
11、ead 8 6 I2C Block Write 9 7 I2C paging mechanism 11 8 SAVE_N trigger mode timing diagram 70 Tables 1 Required SPD fields 13 2 Firmware image header 21 3 Temperature value bit definition 23 4 Page 0 categories 24 5 Page 0 register map 25 6 Timing 69 7 Page 1 categories 71 8 Page 1 register map 71 9 P
12、age 2 categories 79 10 Page 2 register map 79 11 Page 3 categories 89 12 Page 3 register map 89 JEDEC Standard No. 245A -ii- Foreword This standard has been prepared by JEDEC. The purpose of this standard is definition of an energy backed byte addressable function on a non-volatile dual in-line memo
13、ry module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM. Introduction NVDIMM is a DDRbased memory module that can be integrated into a standard platform. An Energy Backed Byte Addressable Function on a NVDIMM is
14、designed to preserve data in the event of the power failure. An Energy Backed Byte Address Function is backed by a combination of SDRAM and non-volatile memory (e.g., NAND flash) on the NVDIMM. It operates at DDR speeds and can provide persistent storage by backing up the SDRAM contents into the non
15、-volatile memory in the event of a power failure. This is made possible by an Energy Source (e.g., super-capacitor) which maintains charge on the module enabling back-up of data from SDRAM to the non-volatile memory, providing a storage-class memory solution. To be able to provide interoperability a
16、nd the ability for platform and platform software (e.g., BIOS) to support NVDIMMs from various manufacturers, standardization of the host to module interface, discovery mechanism, the feature set and command operations are required, as described in this document. JEDEC Standard No. 245A Page 1 BYTE
17、ADDRESSABLE ENERGY BACKED INTERFACE (From JEDEC Board Ballot JCB-16-25, formulated under the cognizance of the JC-45.6 Subcommittee on Hybrid Modules. Item 2233.22) 1 Scope This standard specifies the host and device interface for a DDR4 DIMM interface module that achieves non-volatility by copying
18、SDRAM contents into non-volatile memory when Host power is lost using an Energy Source managed by either the module or the Host. Although this standard is targeted towards DDR4 NVDIMM only, it does not preclude adoption of this standard by other implementations (e.g., DDR3 NVDIMM). 2 Normative Refer
19、ences The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this standard are
20、encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated. For undated references, the latest edition of the normative document referred to applies. DDR4 SPD Contents NVDIMM Revision 0.5 JESD21C, SPD4_01_06, EE1004 and TSE2004 Device Specific
21、ation I2C Bus Specification Revision 4 System Management Bus (SMBus) Specification Version 2.0 DDR4 RCD02 Specification DDR4 DB02 Specification JEDEC Standard No. 245A Page 2 3 Terms and definitions For the purposes of this standard, the terms and definitions given in the document included in clause
22、 2 “Normative References” and the following apply: 3.1 Acronyms DDR3 Double Data Rate version 3 DDR4 Double Data Rate version 4 NVM Non-Volatile Memory DIMM Dual In-line Memory Module NVDIMM Non-volatile Dual In-line Memory Module SPD Serial Presence Detect I2C Inter-IC ES Energy Source SDRAM Synchr
23、onous Dynamic Random Access Memory LCOM LCOM Bus RCD Registering Clock Driver 3.2 Terms and definitions Abort: Operation that stops the currently running operation on the module. See 7.1.9 for more information. Arm: Operation that enables or disables trigger(s) for a Catastrophic Save operation. See
24、 7.1.4 for more information. Catastrophic Save: Process of copying the SDRAM contents into non-volatile memory when power is lost. The Catastrophic Save operation is initiated when an enabled trigger occurs or a write to an I2C register. See 7.1.1 for more information. Device Managed Policy: Energy
25、Source policy where the module manages the Energy Source used during the Catastrophic Save operation. Energy Source: A device that is capable of storing and providing energy to the module during a Catastrophic Save operation. Erase: Operation that deletes the previously saved SDRAM content in non-vo
26、latile memory. See 7.1.3 for more information. Factory Default: Operation that erases all non-volatile memory on the module and resets readable registers to its factory default value except the data needed to determine warranty compliance. This operation does not impact firmware on the module. See 7
27、.1.10 for more information. Firmware Operations: Operations that are related to updating the firmware on the module. See 7.1.8 for more details. JEDEC Standard No. 245A Page 3 3.2 Terms and definition (contd) Host: The system in which the module is installed in. Host Managed Policy: Energy Source po
28、licy where the Host manages the Energy Source used during the Catastrophic Save operation. I2C Bus: A bidirectional 2-wire bus for efficient inter-IC control. LCOM: A local communication bus, bidirectional 6-wire interface that connects the module non-volatile controller to other components. Managem
29、ent Operations: Operations that either reset the controller on the module or clear status register(s). See 7.1.5 for more details. Restore: Process of restoring previously saved SDRAM contents from non-volatile memory to SDRAM. See 7.1.2 for more information. Self-refresh: The SDRAM state that maint
30、ains data integrity without requiring any host interaction. SDRAM Mode Registers: The registers on SDRAM that configures the SDRAM for operational use. Some of the mode registers are write-only registers. Set Energy Source Policy: Operation that configures the Energy Source to be used by the module
31、in the Catastrophic Save operation. See 7.1.6 for more details. Set Event Notification: Operation that either enables or disables notification support on the module when certain event occurs. See 7.1.7 for more details. Typed Block Data: A collection of data that is transferred between the Host and
32、module in 32 bytes increment. Vendor Log Page: An optional area on the module that is accessible by the Host and containing vendor specific data useful to triage issues on the module. See 7.10 for more details. 3.3 Keywords Several keywords are used to differentiate levels of requirements and option
33、s, as follow: Can - A keyword used for statements of possibility and capability, whether material, physical, or causal (can equals is able to). Expected - A keyword used to describe the behavior of the hardware or software in the design models assumed by this standard. Other hardware and software de
34、sign models may also be implemented. Ignored - A keyword that describes bits, bytes, quadlets, or fields whose values are not checked by the recipient. JEDEC Standard No. 245A Page 4 3.3 Keywords (contd) Mandatory - A keyword that indicates items required to be implemented as defined by this standar
35、d. May - A keyword that indicates a course of action permissible within the limits of the standard (may equals is permitted). Must - The use of the word must is deprecated and shall not be used when stating mandatory requirements; must is used only to describe unavoidable situations. Optional - A ke
36、yword that describes features which are not required to be implemented by this standard. However, if any optional feature defined by the standard is implemented, it shall be implemented as defined by the standard. Reserved - A keyword used to describe objectsbits, bytes, and fieldsor the code values
37、 assigned to these objects in cases where either the object or the code value is set aside for future standardization. Usage and interpretation may be specified by future extensions to this or other standards. A reserved object shall be zeroed or, upon development of a future standard, set to a valu
38、e specified by such a standard. The recipient of a reserved object shall not check its value. The recipient of a defined object shall check its value and reject reserved code values. Shall - A keyword that indicates a mandatory requirement strictly to be followed in order to conform to the standard
39、and from which no deviation is permitted (shall equals is required to). Designers are required to implement all such mandatory requirements to assure interoperability with other products conforming to this standard. Should - A keyword used to indicate that among several possibilities one is recommen
40、ded as particularly suitable, without mentioning or excluding others; or that a certain course of action is preferred but not necessarily required; or that (in the negative form) a certain course of action is deprecated but not prohibited (should equals is recommended that). Will - The use of the wo
41、rd will is deprecated and shall not be used when stating mandatory requirements; will is only used in statements of fact. 3.4 Conventions This standard uses the following conventions: A binary number is represented in this standard by any sequence of digits consisting of only the Western-Arabic nume
42、rals 0 and 1 immediately followed by a lower-case b (e.g., 0101b). Spaces may be included in binary number representations to increase readability or delineate field boundaries (e.g., 0 0101 1010b). A hexadecimal number is represented in this standard by any sequence of digits consisting of only the
43、 Western-Arabic numerals 0 through 9 and/or the upper-case English letters A through F immediately followed by a lower-case h (e.g., FA23h). Spaces may be included in hexadecimal number representations to increase readability or delineate field boundaries (e.g., B FD8C FA23h). JEDEC Standard No. 245
44、A Page 5 3.4 Conventions (contd) A decimal number is represented in this standard by any sequence of digits consisting of only the Western-Arabic numerals 0 through 9 not immediately followed by a lower-case b or lower-case h (e.g., 25). A range of numeric values is represented in this standard in t
45、he form “a to z“, where a is the first value included in the range, all values between a and z are included in the range, and z is the last value included in the range (e.g., the representation “0h to 3h“ includes the values 0h, 1h, 2h, and 3h). When the value of the bit or field is not relevant, x
46、or xx appears in place of a specific value. From this point on the content and organization of the document can take different forms depending upon the purpose of the document. Committees are encouraged to develop formats for those types of documents that they prepare repetitively. Most will be orga
47、nized by clauses and subclauses. Some will benefit from the use of annexes and/or an index. These elements are explained in the following. JEDEC Standard No. 245A Page 6 4 Introduction For modules containing both SDRAM and non-volatile memory, a non-volatile DIMM (NVDIMM) can be created if the conte
48、nts of the SDRAM can be persisted to the non-volatile memory when power is lost using an alternative power source and the contents of the SDRAM restored when power is available. This type of NVDIMM is classified as one that supports the Byte Addressable Energy Backed Interface. This specifications d
49、efines the host and device interface for a DDR4 DIMM interface module that implements the Byte Addressable Energy Backed Interface. The module achieves non-volatility by copying SDRAM contents into non-volatile memory when Host power is lost using an Energy Source managed by either the module or the Host. The Byte Addressable Energy Backed Interface is controlled by the Host through a set of I2C registers using the standard I2C Bus implemented through the SCL and SDA pins on the DDR4 bus. Centralized Energy Source power is provided through the 12V pin on the DDR4 bus. E ne r gy S ou r
