1、EIA JESD55 b 3234600 057L7L.5 OB0 1811 EINJl3DEC STANDARD Standard for Description of Low-Voltage TTL-Compatible BiCMOS Logic Devices EIAiJESD55 MAY 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesIA JESD5
2、5 96 W 3234bOO 0573736 TI7 = NOTICE EWJEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EL4 General Counsel. EWJEDEC Standards and Publications are designed to s
3、erve the public interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such sta
4、ndards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not mnfonning to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EM members, whether the standard is to be used either domestica
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6、es adopting the EWJEDEC Standards or Publications. The information included in EWJEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the EIA/JEDEC organization there are proCsdur
7、es whereby an EWJEDEC Standard or Publication may be further processed and ultimately becomes an ANSVELA Standard. Inquiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EL4 Headquarters, 2500 Wilso
8、n Boulevard, Arlington, VA 2220 1. Published by OELECTRONIC INDUSTRIES ASSOCIATION 1996 Engineering Department 2500 Wilson Boulevard Arlington, VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JED
9、EC Publication 2 1 “Manual of Organization and Procdure“. PRICE: Please refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved
10、COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD.55 96 3234600 05LL 953 W JEDEC STANDARD No. 55 Page 1 Standard for Description of Low-Voltage lTL-Compati ble BICMOS Loglc Devices (From JEDEC Council Ballot, JCB-95-66, formulated under the cognizance of the J
11、C-40 Committee on Standardidion of Digital Logic) 1 INTERFACE STANDARD 1.1 Purpose: To provide a standard for Low-Voltage BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users, 1.2 Scope: This standa
12、rd defines dc interface and switching parameters for a high-speed, low-voltage BiCMOS digital logic family. This standard covers specifications for BiCMOS Logic series as defined in Section 2. 2 DEFINmONS BiCMOS Series Includes devices combining bipolar and silicon-gate complementary metal-oxide-sem
13、iconductor (CMOS) field effect devices in a single-chip integrated circuit. Includes devices whose input logic levels are TTL compatible, whose outputs are specified at TTL levels. Compliant with current revision of JEDEC standard 8-A. Prefixes Prefix 74“ immediately preceding family name indicates
14、the operating temperature range. 74XXX refers to the Commercial (COML) version of devices which are specified over40“C to 85C. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD55 9h 3234b00 0571718 B9T Symbol VDD VIN VOUT TA AVAv JEDEC STANDARD No. 55 Page 2 P
15、arameter Supply voitage (Note 1 ) Input Vdtage Output voltage (Note 2) operating fm4r temperature input transition rise or fail rate (Note 3) 3 STANDARD SPECIFICATIONS 3.1 Supply Voltage, VDD 4.5 V to 4.6 V dc input voltage, VI (Note 3) . -0.5 V to 7 V dc output voltage, VO -0.5 V to 5.5 V dc input
16、clamp current, IIK (VI O) . -18 mA dc output clamp current, OK (Vo O) . -30 mA * IOL( rated) dc current into any output in the low state, IOL (Note 4) dc current into any output in the high state, IOH (Note 5) 2 lOH(rated) Storage temperature range -65C to 150C Absolute Maximum Continuous Ratings (N
17、otes 1 and 2): . Note I: Absdute maximum continuous ratings are those Values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not imp
18、lied. Under transient conditions these ratings may be exceeded as defined elsewhere in this speafication. The dc inpu negative voltage rating may be exceeded if the dc input clamp current ratings are observed. Not to exceed 70 mA. Not to exceed -35 mA. Note 2: Note 3: Note 4: Note 5: 3.2 Recommended
19、 Operating Conditions: COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESB5.5 %b U 3234600 057L7L 726 JEDEC STANDARD No. 55 Page 3 3.3 dc SDecifications: Symbol VIH VIL VIK “OH “OL I IH IL OZH Test CondWlons I I HigMevel input voltage 2 Low-level input voitage I
20、nput clamp voltage VDD = MIN, il = -18 mA HlgMevd cuipul voltage Low-level ouipui voltage 2.4 2 2 input current Low-level inputcurrent VDD = MAX. 1 VI = 0.5 V pons VDD = MAX, vo 5.5 v 1 m-stam output current VDD = MAX. except poits (Note i) VO = 0.5 V 110 ports 1 0.8 il 5 COPYRIGHT Electronic Indust
21、ries AllianceLicensed by Information Handling ServicesEIA JESD55 96 = 3234600 0573720 448 W Symbol Parameter Bus-hol low sustaining current Bus-hoM high sustaining current Buc-hdd low overdrive Bus-hoid high overdrive current Static supply current, one output in the high- impedance state Static supp
22、ly current, Static supply current Stak supply current per input at a IBHLO current DDZ IDDH one output high $DL outputslow *IDD specified levei JEDEC STANDARD No. 55 Page 4 74 seriea MIN MAX Test Conditions Unit VDD = 3 V, VI = 0.8 V, (Note 3) 75 ClA VDD = 3 V, VI = 2 V, (Note 4) -75 iIA VDD = 3.6 V
23、, (Note 5) 500 PA VDD = 3.6 V, (Note 6) -500 PA VDD = MAX. 25 VI = VDD 01 GND (Note7) PA VDD = MAX, 25 VI = VDD or GND (Note 7) PA (Note2) mA VDD = MAX, VI = VDD or GND 0.2 mA VI = VDD - 0.6 V. other inputs at VDD or GND. VDD = MIN to MAX COPYRIGHT Electronic Industries AllianceLicensed by Informati
24、on Handling ServicesEIA JESD55 76 H 3234600 05711723 384 Generator I JEDEC STANDARD No. 55 Page 5 = CL 4 TEST CIRCUITS AND SWITCHING WAVEFORMS Test tpLH (except open-collector outputs) Switch Open t PZH t PZL tPHZ 6V OPEN GND GND 6V GND I tPLH (open-collector outputs) I 6V I I tPHL (except open-coii
25、ector outputs) I Open I I tPHL (open*oiiector outputs) I 6V I I i tPL2 6V I CL = 50 pF or equivalent (includes jig and probe capacitance). AL = A1 = 500 nor equivalent. AT = %UT of pulse generator (typically 50 n). COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesJEDE
26、C STANDARD No. 55 Page 6 PROPAGATION DELAY MEASUREMENTS PULSE DURATION (WIDTH) MEASUREMENTS Hig Mevel Input Pulse Low-level Input Pulse /-I- - - - - - - - 2.7 V 1.5 V ov 2.7 V 1.5V ov Output requirements: Device must follow truth table VOL I VOL max VoZVomin t, = tf = 2.5 ns (or as fast as required)
27、 from 10% to 90% of O V to 2.7 V. Input Conditions: COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESP55 Yb 3234600 8573723 157 m JEDEC STANDARD No. 55 Page 7 SETUP AND HOLD TiME MEASUREMENTS Synchronous Control I ENABLE TIME MEASUREMENTS ourput High-Z to LOW C
28、OPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD55 96 3234600 0573724 093 JEDEC STANDARD No. 55 Page 8 DISABLE TIME MEASUREMENTS Enable Input output High to High-Z COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services EIA JESD.55 9b
29、 3234600 0573725 T2T = JEDEC STANDARD No. 55 Page 9 5 SUPPLY CURRENT TEST PROCEDURES This section contains the test measurement procedure and test conditions to be used when measuring IDDL on BiCMBS logic devices. A description of the symbols used follows the table. Refer to Sections 3.3 and 3.4 for
30、 other IDD measurement parameters. Note: The above symbols are interpreted as follows: H = VDD L = GND (O V) M = Force VDD Measure IDD X = Dont care; VDD or GND, but not switching = GND (O V) o=open COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD55 76 U 3234
31、600 0573726 7bb M JEDEC STANDARD No. 55 Page 10 I I Pin Number I Note: The above symbois are interpreted as follows: H = VDD L = GND (O V) M = Force VDD Measure IDD 2.7 V - CE ClWkplW n - GND X = Dont care; VDD or GND. but not switching G = GND (O V) O = Open COPYRIGHT Electronic Industries Alliance
32、Licensed by Information Handling ServicesEIA JESD55 96 3234600 0573727 IT2 m JEDEC STANDARD No. 55 Page 11 6 SWITCHING SPEED STANDARDS This section establishes standard maximum limits for switching parameters and minimum limits for timing parameters for the device types listed herein. For parameter
33、measurement information, refer to Section 4. Refer to individual manufacturers datasheets for applicable minimum limits for switching Standardized limits for switching parameters (dynamic characteristics) are specified by pari parameters. identifiers in numeric order. 6.1 Index of device types: Buff
34、ers and Drivers: 125, 240,244, 16244, 162244(16244-1) Latches and Flip-Flops: 273, 573,574 16373,16374 Transceivers: 245, 16245,162245,16245-1 Registered Transceivers: 543 646,652,2952 16500,16501,16543,16646 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD55
35、 96 3234600 0573728 739 = 4 JEDEC STANDARD No. 55 Page 12 4.9 ns 6.2 Switching speed tables: Buffers and Drivers: 125 I Device ISymbol IPerameter tpLH PHL zr Maximum propagation delay, A to Y Maximurn output enable delay, G to Y I tpHz tPU 1 Maximum output disable delay, G to Y 1: I Maximum propagat
36、ion delay, A to Y _ _ 240 Maximum output enable delay, G to Y Maximum output disable delay, G to Y tpHZ tPL2 1 1 Maximum propagation delay, A to Y 244 Maximum output enable delay, G to Y Maximum output disable delay, G to Y tPHZ I tpLH Maximurn propagation delay, A to Y I PHL I I 16244 I $fp I Maxim
37、um output enable delay, G or to Y tpHZ Maximum output disable delay, G or 0 to Y I ItPY I I tpLH Maumum propagation delay, A to Y I PHL I . . .- I 162244 I. I I lPZH I Maximum output enable delay, G o( 0 to Y I I I tpHZ I Maximum output disable delay, G o( to Y t PU 74 Series I Units 3.3VI0.3V 12.7V
38、 I I 1 4.7 6.5 ns I 5.1 15.7 Ins I “1 5.2 I ns 5.6 16.3 5.6 16.3 11-18 -1 4. f 15.2 Ins I 5.2 76.7 Ins , 5.7 76.3 Ins I 11 6.4 6.6 7.3 ns I COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESDCS clb II 3234600 O573729 675 Dsvlca JEDEC STANDARD No. 55 Page 13 74 s
39、wlea Unib 3.3 V f 0.3 V I 2.7 V Symbol Paramstar Latches and Flip-Flops: tpLH PHL tpHL tsu th Maximum propagation delay, CLK to O 5.5 6.3 ns Maximum propagation delay, CLR to Q 5.1 6.2 Ils D before CLK? 2.3 2.7 ns Minimum setup time CLA inactive before CLK? 2.7 3.2 ns Minimum hold Ume, D after CLKt
40、O O ns 273 Maxlmum outpul enable delay, G to Q Maximum outpui disable delay, G to Q Minimum setup time, D before CLKT Minimum hokl time, D after CLK? Minimum pulse uratlon, CLK high or low 5.1 6.2 ns 5.5 5.9 ns 2 2.4 Ils 0.3 O Ils 3.3 3.3 Ils 574 tPHL tH t PZH t PZL I I Dto Q 5 15.7 ns C to Q 6.9 18
41、.8 I ns wmum propegatkn eiay Fv WH tPZL tz ltpll tsu ol tW Maxlmum propegation delay, Cu to Q I Meximum output me delay, G to a 5.3 6.3 Ils aximwn disable delay, to a 6.8 7.6 ns Minimum setup Ume, D before LEI 0.5 0.5 ns 1iRMmum hold Ume. D after LEI 1.8 2 ns Mnimwn puke durah. LE high 3.3 3.3 ns 15
42、.9 16374 I I I tpHz I Maximum output disable delay, G to Q 6.8 7.6 ns tPLZ Minimum setup time, D before CLK? Minimum hold time, D after CLKf Minimum pulse duration, CLK high or low 16373 I I 2.2 2.6 ns 0.6 O ns 3.3 3.3 ns I I Maximum propegation delay, CLK to a 16.6 17.2 1 ns I I :F:L 1 Maximum ouip
43、ut enable delay, to Q 15.3 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESD55 96 323YbOO 0573730 397 Symbol JEDEC STANDARD No. 55 Page 14 74 series I nb Paramater 3.3 V f 0.3 V I 2.7 V I Transceivers: Maximum propagation delay, A or B to B or A Maximum output
44、 enable delay, G to A or B Maximum output disable delay, G to A or B 1- Device 4 5.5 5.9 245 Maximum output enable delay, G to A or B Maximum output disable delay. G to A or B - 16245 J 5.3 6.7 ns 6.4 7.2 ns 162245 or 16245-1 Maximum propagation delay, A to Maximum propagation delay, B to A Maximum
45、output enable delay. G to A or B 4.1 5.2 ns 5.5 6.9 ns 7.2 9.4 ns tPHZ tPl2 Maximum propagation delay, A or B to B or A 14.1 I Maximum output disable delay, G to A or B 7.3 8 ns qg 5.2 COPYRIGHT Electronic Industries AllianceLicensed by Information Handling Services EIA JESD.55 76 111 3234b00 057173
46、1 223 111 Device JEDEC STANDARD No. 55 Page 15 74 *ka 3.3 V f 0.3 V 12.7 V I 174 series I Units Symbol Parameter Registered Transceivers: I 543 tpHz t PU tsu 4i tW Maximum ouiput disable delay, G or Minimum setup Ume, A or B before LE? or CE? Minimum hold time, A or B after LE? or CE? Minimum pulse
47、duration, LE or CE low to A or B I tpLH PHL I Maximum propagation delay C I tsu th tW Minimum setup time, A before CAB? or B before CBA? Minimum hold time, A after CAB? or B aiter CBA? Minimum puise duration, CAB or CBA A to B or B to A LEAB or LEBA to B or A A or B to B or A CAB or CBA to Bor A SAB
48、 or SBA to B or A Maximum propagation delay tPHL PZH tP2L tpHz tPY tsu 4i tW PLH tFWL tpZH t PZL mimum output enable delay, GBA or GAB to A or B Maximum output disable delay, %A or GAB to A or B Minimum setup time, A before CAB? or B before CBAt Minimum hold tim. A after CABt or B after CBA? Minimum
49、 pulse duration. CAB or CBA mimum propagation way, CAB or CBA to B or A Maximum output enable delay, GBA or GAB to A or B 652 I I I Maximum output disable delay, G or to A or B I l 4.7 5.5 ns 6 6.9 ns 6.4 7.6 ns 6.5 7.5 ns 7.2 8.1 ns 2 2.5 ns 0.5 0.5 ns 3.3 3.3 ns 6.1 7.1 ns 6.5 8 ns Minimum setup time, A before CABt or B before CBAT before CAB? or 8 before CeA? A or B to B or A CAB or CBA to B or A CAB or SBA to B or A 2.5 2.8 ns 2.4 . 2.7 ns G to A or B DIR to A or B tpZH Maxlmum output enable delay C th I I I 646 I *-.
