1、JEDEC STANDARD Standard for Description of 3877: 2.5 V, Dual 5-Bit, 2-Port, DDR FET Switch JESD73-4 NOVEMBER 2001 _ JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors le
2、vel and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the
3、 purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve p
4、atents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound app
5、roach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further processed and ultimately become an ANSEIA standard. No claims to be in conformanc
6、e with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834
7、, (703)907-7559 or www.jedec.org Fublished by OJEDEC Solid State Technology Association 200 1 2500 Wilson Boulevard Arlingtq VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charg
8、e for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada 1-800-854-7179, International (303) 397-7956 Printed in the U.S.A. All rights reserved JEDEC Standard No. 73-4 Page
9、1 Standard for description of 3877: 2.5 V, Dual 5-bit, 2-p0rt, DDR FET switch (From Board Ballot JCB-01-62, formulated under the cognizance of the JC-40.2 Subcommittee on Bus Switch Logic Products.) 1 Scope This standard covers the specification for the 3877, 2.5 V, FET transmission-gate bus switch
10、device with 2.5 V LVTTL compatible control inputs. Not included in this document are device specific parameters and performance levels that the vendor must also supply for the full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the descripti
11、on of the 3877, 2.5 V, DDR FET switch device. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of the 3877, 2.5 V, DDR FET switch device. NOTE The designation 3877 refers to the numerical portion of the part designation of
12、a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation. 2 Definitions for the purpose of this document switch device: A semiconductor logic device designed to connect or discon
13、nect busses or control signals without active drivers in the connection path. connect: A state in a switch device is characterized by a minimum series impedance through the designated electrical path. disconnect: A state in a switch device is characterized by the high series impedance of the designa
14、ted electrical path. JEDEC Standard No. 73-4 Page 2 3 Standard specification 3.1 Device description This IO-bit, tweport bus switch is designed for 2.3 V to 2.7 V, VDD operation. All inputs are compatible with the JEDEC standard for 2.5 V, CMOS. The 3877 device is organized into two banks of 5-bit,
15、transmission-gate bus switches. Each bank is enabled through an associated Bus Enable (E), which is driven low to enable the switches and connect the Aport to the B-port. Driving BE high will disable the switches and disconnect the A-port from the B-port with a high impedance state. The 3877, is int
16、ended to be used with X4 SDRAM memory. The fifth transmission gate in each provides a path for overhead data. The bus enableK pins do not have an internal pull-up resistor. The output pins on the B-side of the device are pulled down to ground reference through a weak resistor structure to provide te
17、rmination to the transmission gate switch channels. Package options for this device include thin small-outline package (MO-153 AD). 3.2 Logic block diagram and device pin configuration Figure 1 - Logic block diagram Figure 2 - Device pin configuration JEDEC Standard No. 73-4 Page 3 AO-9 BO-9 GND VDD
18、 3 Standard specification (contd) 3.3 Product pin description and truth table A-port B-port Ground Power Table 1 - Device tin descrirtion Supply voltage range, VDD DC input voltage Bus I/O Voltage to Ground Potential I Pin Name I Description I -0.5 V to +3.6 V -0.5 V to +3.6 V -0.5 V to +3.6 V IBEO,
19、BEl I Bus Enable Input (Active LOW) I Table 2 - Loaic Truth Table I Function I Disconnect I H I AO-AA I Hi-Z B&B4 I I Connect IL I BO-B4 AO-A4 I I Function I Disconnect I H I Connect IL I AS-Ag I Hi-Z I B5-B9 Tab1 BSB9 I A5-A9 I H = High Voltage Level L = Low Voltage Level Hi-Z = High Impedance 3.4
20、Absolute maximum ratings DC channel current 1128 mA Storage temperature 65 “C to 150 “C Note) NOTE Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions a
21、bove those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. JEDEC Standard No. 73-4 Page 4 VDD TA 3 Standard specification (contd) 3.5 Recommended operating conditions Supply Voltag
22、e 2.3 2.7 V O +70 “C Ope rat in g Free- Air temperature Table 4 - Recommended oreratina conditions fsee Note High -Level input voltage VI H I Parameter I Description I Min. I Max. I Units I Guaranteed Logic level High .6 I Low-level NOTE Unused device control inputs must be held at VDD or GND to ens
23、ure proper device operation. 3.6 DC electrical specifications Table 5 - Electrical characteristics over recommended operating free-air temperature range Parameter I Description I Test Conditions* I Min I Typ: I Max. I Units I I Guaranteed Logic level Low Clamp Diode Voltage High Impedance output Cur
24、rent VI K IOZH VDD = Min., IIN = -1 8 mA BE =H B-Port I/O level = 2.5V - 250 PA I 0.9 I v Switch ON Resistance* RON I -1.2 I v 17 33 Q 22 30 Q VDD = Min., VIN = 0.9 V, ION = 20 mA VDD = Min., VIN = 1.6 V, ION = 15 mA * Characteristics for the applicable device type. For Max. or Min. conditions, use
25、appropriate value specified under Electrical t Typical values are at VDD = 2.5 V, TA = 25 “C ambient and maximum loading. $ Measured by the voltage drop between A and B pin at indicated current through the switch. ON resistance is determined by the lower of the voltages on the two (A,B) pins. JEDEC
26、Standard No. 73-4 Page 5 CON (AB) 1 AB Capacitance, Switch ON I VIN = 0 v 3.6 DC electrical specifications (contd) 7.0 PF Table 6 - Capacitance I I I I I I Min. Typ. Max. Test Parameter Conditions*$ VDD = max - - 10 Quiescent power IDD supply current l Parateter Units UA I Description Comm. Min. Max
27、. 1 3 1 3.5 1 3 1 3.8 Parameter Description Test Conditions Bus Enable Time BE to Ax or Bx = High Bus Enable Time BE to Ax or Bx = Low tPZL tPHZ Bus Disable Time BE to Ax or Bx =High Bus Disable Time BE to Ax or Bx =Low tPZH CL = 30 pF, RL = 500 Q tP LZ Test 1 Max. 1 Units 1 1 Conditions Units ns I
28、CIN I Input Capacitance rl A Capacitance, Switch OFF I VIN = OV I 3.0 I pF I 3.7 AC Specifications JEDEC Standard No. 73-4 Page 6 4 Parameter measurements Load Circuit Voltage waveforms propagation delay times Vo It age waveforms Enable and disable times Figure 3 - Parameter measurements NOTE 1 CL i
29、ncludes probe and jig capacitance. NOTE 2 Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. NOTE 3 All input pulses are supplied by generators having the following characteristics: PRRc10 MHz, Z, = 50 Q, tR 2 2 ns, tF 2 2 ns. NOTE 4 The outputs are measured one at a time with one transition per measurement.
