1、JEDEC STANDARD PSO-N/PQFN Pinouts Standardized for 14-, 16-, 20-, and 24-Lead Logic Functions JESD75-6 MARCH 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors leve
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6、h this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid S
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8、 to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obta
9、in permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 75-6 Page 1 PSO-N/PQFN PINOUTS STANDARDIZ
10、ED FOR 14-, 16-, 20-, AND 24-LEAD LOGIC FUNCTIONS (From JEDEC Board Ballot JCB-05-151, formulated under the cognizance of the JC-40 Committee on Digital Logic) 1 Scope This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to th
11、e conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices. The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of
12、 confusion, ease of device specification, and ease of use. 2 Terms and definitions For the purposes of this standard, the following apply: DIP: Dual In-line Pin Package HW-PQFP/HV-PQFP/PSO-N: Dual Compatible Thermally Enhanced Plastic Very Thin and Very Very Thin Fine Pitch Quad Flat No Lead Package
13、 (MO-241 Issue B, variations AA, BA (14-lead), AB, BB (16-lead), and AC, BC (20-lead) HWF-PQFN/HVF-PQFN: Thermally Enhanced Plastic Very Thin and Very Very Thin Fine Pitch Quad Flat No Lead Package (MO-220 Issue J, variations VGGD-2 and VGGD-8 (24-lead) 3 Pinout standard 3.1 Description The followin
14、g criteria shall be used to convert existing 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-pin DIP packages to 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages. JEDEC Standard No. 75-6 Page 2 3 Pinout standard (contd) 3.2 14-lead PSO-N (MO-241, Variation AA, BA) Figure 1 Pi
15、n configuration for MO-241, variation AA, BA (bottom view) 3.2 Pin conversion from 14-pin DIP to 14-lead PSO-N The pin conversion adopts the naming convention of the logic devices in the 14-pin DIP packages. Pin Number 14-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 1414-lead PSO-N 1 2 3 4 5 6 7 8 9 10 11
16、12 13 14Figure 2 14-lead pin conversion table JEDEC Standard No. 75-6 Page 3 3 Pinout standard (contd) 3.3 16-lead PSO-N (MO-241, Variation BA, BB) Figure 3 Pin configuration for MO-241, variation BA, BB (bottom view) 3.4 Pin conversion from 16-pin DIP to 16-lead PSO-N The pin conversion adopts the
17、naming convention of the logic devices in the 16-pin DIP packages. Pin Number 16-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1616-lead PSO-N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Figure 4 16-lead Pin Conversion Table JEDEC Standard No. 75-6 Page 4 3 Pinout standard (contd) 3.5 20-lead PSO-N (MO-241,
18、 variation AC, BC) Figure 5 Pin configuration for MO-241, variation AC, BC (bottom view) 3.6 Pin conversion from 20-pin DIP to 20-lead PSO-N The pin conversion adopts the naming convention of the logic devices in the 20-pin DIP packages. Pin Numbers 20-pin DIP 1 2 3 4 5 6 7 8 9 10 20-lead PSO-N 1 2
19、3 4 5 6 7 8 9 10 20-pin DIP 11 12 13 14 15 16 17 18 19 20 20-lead PSO-N 11 12 13 14 15 16 17 18 19 20 Figure 6 20-lead pin conversion table JEDEC Standard No. 75-6 Page 5 3 Pinout standard (contd) 3.7 24-lead PQFN (MO-220, variations VGGD-2 AND VGGD-8) Figure 7 Pin configuration for MO-220, variatio
20、ns VGGD-2 and VGGD-8, (bottom view) 3.8 Pin conversion from 24-pin DIP to 24-lead PQFN The pin conversion adopts the naming convention of the logic devices in the 24-pin DIP packages. Pin Numbers 24-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 24-lead PQFN 1 2 3 4 5 6 7 8 9 10 11 12 24-pin DIP 13 14 15 16 17
21、18 19 20 21 22 23 24 24-lead PQFN 13 14 15 16 17 18 19 20 21 22 23 24 Figure 8 24-lead Pin Conversion Table JEDEC Standard No. 75-6 Page 6 4 Reference to other applicable JEDEC standards and publications JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Product STANDARD IMPRO
22、VEMENT FORM JEDEC JESD75-6 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate
23、committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the following: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date:
