1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD820AOCTOBER 2009JEDECSTANDARDPOD15 1.5V Pseudo Open Drain I/O(Revision of JESD8-20, December 2006) NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board of Directors level and subseque
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5、on and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard orpublication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made u
6、nless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC at the address below, or call (703) 9077559 orwww.jedec.orgPublished byJEDEC Solid State Technology Association 2009310
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8、n the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Association and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For
9、 information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240 SouthArlington, Virginia 22201-2107JEDEC Standard No, 820APage 1POD15 1.5V PSEUDO OPEN DRAIN I/O(From JEDEC Board ballot JCB0971, formulated under the cognizance of the JC16 Committee on Voltage Level and
10、 Electrical Iterface.)1 ScopeThis standard defines the dc and ac singleended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily use
11、d to communicate with GDDR4 and GDDR5 SGRAM devices.JEDEC Standard No. 820APage 22 Operating conditions NOTE 1 GDDR4 and GDDD5 SGRAMs are designed to tolerate PCB designs with separate VDD and VDDQ power regulators.NOTE 2 AC noise in the system is estimated at 50mV pkpk for the purpose of DRAM desig
12、n.NOTE 3 Source of Reference Voltage and control of Reference Voltage for DQ and DBI# pins is determined by VREFD, Half VREFD, Auto VREFD, VREFD MERGE and VREFD Offsets mode registers.NOTE 4 VREFD Offsets are not supported with VREFD2.NOTE 5 External VREFC is to be provided by the controller as ther
13、e is no other alternative supply.NOTE 6 DQ/DBI# input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC).NOTE 7 ADR/CMD input slew rate must be greater than or equal to 3V/ns. The s
14、lew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC).NOTE 8 VIHX and VILX define the voltage levels for the receiver that detects x32 or x16 mode with RESET# going High.NOTE 9 Applicable to GDDR4 or other interface with a single VREF for the device.NOTE 10 Applicable to GDDR5 or othe
15、r interface with multiple VREF pins and levels.Table 1 DC Operating ConditionsPOD15Parameter Symbol Min Typ Max Unit NoteDevice Supply Voltage VDD 1.455 1.5 1.545 V 1Output Supply Voltage VDDQ 1.455 1.5 1.545 V 1Reference Voltage VREF 0.69 * VDDQ 0.71 * VDDQ V 2, 9Reference Voltage for DQ and DBI# p
16、ins VREFD 0.69 * VDDQ 0.71 * VDDQ V 2, 3, 10Reference Voltage for DQ and DBI# pins VREFD2 0.49 * VDDQ 0.51 * VDDQ V2, 3, 4, 10External Reference Voltage for address and commandVREFC 0.69 * VDDQ 0.71 * VDDQ V 5, 10DC Input Logic HIGH Voltage VIH (DC) VREF + 0.12 V 9DC Input Logic LOW Voltage VIL (DC)
17、 VREF 0.12 V 9DC Input Logic HIGH Voltage for address and commandVIHA (DC) VREFC + 0.15 V 10DC Input Logic LOW Voltage for address and commandVILA (DC) VREFC 0.15 V 10DC Input Logic HIGH Voltage for DQ and DBI# pins with VREFDVIHD (DC) VREFD + 0.10 V 10DC Input Logic LOW Voltage for DQ and DBI# pins
18、 with VREFDVILD (DC) VREFD 0.10 V 10DC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD2VIHD2 (DC) VREFD2 + 0.30 V 10DC Input Logic LOW Voltage for DQ and DBI# pins with VREFD2VILD2 (DC) VREFD2 0.30 V 10Input Logic HIGH Voltage for RESET#, SEN, MFVIHR VDDQ 0.50 V 10Input Logic LOW Voltage fo
19、r RESET#, SEN, MFVILR 0.30 V 10Input logic HIGH voltage for EDC1/2 (x16 mode detect)VIHX VDDQ 0.3 V 8, 10Input logic LOW voltage for EDC1/2 (x16 mode detect)VILX 0.30 V 8, 10Input Leakage CurrentAny Input 0V = VIN= VDDQ(All other pins not under test = 0V) Il AOutput Leakage Current (DQs are disabled
20、; 0V = Vout = VDDQ)Ioz AOutput Logic LOW Voltage VOL (DC) 0.62 VJEDEC Standard No, 820APage 32 Operating conditions (contd) NOTE 1 Applicable to GDDR4 or other interface with a single VREF for the device.NOTE 2 Applicable to GDDR5 or other interface with multiple VREF pins and levels.Figure 1 Voltag
21、e WaveformTable 2 AC Operating ConditionsPOD15Parameter Symbol Min Typ Max Unit NoteAC Input Logic HIGH Voltage VIH (AC) VREFC + 0.20 V 1AC Input Logic Low Voltage VIL (AC) VREFC 0.20 V 1AC Input Logic HIGH Voltage for address and commandVIHA (AC) VREFC + 0.20 V 2AC Input Logic LOW Voltage for addre
22、ss and commandVILA (AC) VREFC 0.20 V 2AC Input Logic HIGH Voltage for DQ and DBI# pins with VREFDVIHD (AC) VREFD + 0.15 V 2AC Input Logic LOW Voltage for DQ and DBI# pins with VREFDVILD (AC) VREFD 0.15 V 2AC Input Logic HIGH Voltage for DQ and DBI# pins with VREFD2VIHD2 (AC) VREFD2 + 0.40 V 2AC Inpu
23、t Logic LOW Voltage for DQ and DBI# pins with VREFD2VILD2 (AC) VREFD2 0.40 V 2VIL (AC)VIL (DC)VREF DC NoiseVREF DC NoiseVREF + DC NoiseVREF + AC NoiseVIH (DC)VIH (AC)VOHVIN (AC) Provides marginbetween VOL (MAX) andVIL (AC)VDDQVOL (MAX)System Noise Margin (Power/Ground, Crosstalk, Signal Integrity At
24、tenuation)OutputInputNote: VREF, VIH, VIL refer towhichever VREFxx (VREFD, VREFD2, or VREFC) is being used. JEDEC Standard No. 820APage 42 Operating conditions (contd)NOTE 1 This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. DRAM timings relative to CK can
25、not be guaranteed if these limits are exceeded.NOTE 2 For AC operations, all DC clock requirements must be satisfied as well.NOTE 3 The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.NOTE 4 VIDCK is the magnit
26、ude of the difference between the input level in CK and the input level on CK#. The input reference level for signals other than CK and CK# is VREFC.NOTE 5 VIDWCK is the magnitude of the difference between the input level in WCK and the input level on WCK#. The input reference level for signals othe
27、r than WCK and WCK# is either VREFD, VREFD2 or the internal VREFD.NOTE 6 The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross. NOTE 7 The WCK and WCK# input reference level (for timing referenced to WCK and WCK#) is the point at which WCK
28、and WCK# cross. NOTE 8 VREFD is either VREFD, VREFD2 or the internal VREFD.NOTE 9 The slew rate is measured between VREFC crossing and VIXCK(AC).NOTE 10 The slew rate is measured between VREFD crossing and VIXWCK(AC).NOTE 11 Figure 3 illustrates the exact relationship between (CKCK#) or (WCKWCK#) an
29、d VID(AC), VID(DC) and tDVACNOTE 12 Ringback below VID(DC) is not allowed.NOTE 13 tDVACis not measured in and of itself as a compliance specification, but is relied upon in measurement of clock operating conditions and clock related parameters.NOTE 14 Applicable to GDDR5 or other interface with mult
30、iple VREF pins and levels.Table 3 Clock Input Operating ConditionsPOD15Parameter Symbol Min Max Unit NoteClock Input MidPoint Voltage; CK and CK# VMP (DC) VREFC 0.10 VREFC + 0.10 V 1, 6Clock Input Differential Voltage; CK and CK#VID or VIDCK (DC)0.22 V 4, 6Clock Input Differential Voltage; CK and CK
31、# VID or VIDCK (AC)0.40 V 2, 4, 6Clock Input Differential Voltage; WCK and WCK# VIDWCK (DC) 0.20 V 5, 7, 14Clock Input Differential Voltage; WCK and WCK# VIDWCK (AC) 0.302, 5, 7, 14Clock Input Voltage Level; CK, CK#, WCK and WCK# single ended VIN 0.30 VDDQ + 0.30CK/CK# Single ended slew rate CKslew
32、3 V/ns 9WCK/WCK# Single ended slew rate WCKslew 3 V/ns 10, 14Clock Input Crossing Point Voltage; CK and CK#VIX or VIXCK (AC)VREFC 0.12 VREFC + 0.12 V 2, 3, 6Clock Input Crossing Point Voltage; WCK and WCK# VIXWCK (AC) VREFD 0.10 VREFD + 0.10 V2, 3, 7, 8, 14Allowed time before ringback of CK/WCK belo
33、w VIDCK/WCK(AC)tDVACps11, 12, 13, 14JEDEC Standard No, 820APage 52 Operating conditions (contd)Figure 2 Clock WaveformFigure 3 Definition of differential acswing and “time above aclevel” tDVACVIX(AC)CK#CKMaximum Clock LevelMinimum Clock LevelVID (AC)VID (DC)VMP (DC)0VID (AC) MINtDVACtDVAChalf cyclet
34、imeDifferentialInputVoltage(i.e.WCK WCK#,CK CK#)VID (DC) MIN(VID (DC) MIN)(VID (AC) MIN)JEDEC Standard No. 820APage 62 Operating conditions (contd)The Driver and Termination impedances are derived from the following test conditions under worst case process corners:1. Nominal 1.5V (VDD/VDDQ)2. Power
35、the DRAM device and calibrate the output drivers and termination to eliminate process variation at 25 C.3. Reduce temperature to 10 C recalibrate.4. Reduce temperature to 0 C and take the fast corner measurement.5. Raise temperature to 75 C and recalibrate6. Raise temperature to 85 C and take the sl
36、ow corner measurement7. Reiterate 2 to 6 with VDD/VDDQ 1.455V8. Reiterate 2 to 6 with VDD/VDDQ 1.545V9. All obtained Driver and Termination IV characteristics have to be bounded by the specified MIN and MAX IV characteristicsThe following values (Ideal with +/ 10% min/max) are targets for the design
37、er and are not required to be met. Vendor datasheets should be consulted for further details. It is expected that the characteristics of the real curves will have some nonlinearity as shown in Figure 6 and Figure 7. This may help to reduce the overall capacitance and boost performance. It is up to t
38、he designer to find the optimum combination of linearity and capacitance for best Rx and Tx performance. Table 4 1.5V I/O ImpedancesPullDown Characteristic at 40 ohms PullUp/Termination Characteristic at 60 ohmsVoltage (V) MIN(mA) Ideal(mA) MAX(mA) Voltage (V) MIN(mA) Ideal(mA) MAX(mA)0.1 2.52.502.7
39、5 0.11.50 1.67 1.830.2 4.505.005.50 0.23.00 3.33 3.670.3 6.757.508.25 0.34.50 5.00 5.500.4 9.00 10.00 11.00 0.4 6.00 6.67 7.330.5 11.25 12.50 13.75 0.5 7.50 8.33 9.170.6 13.50 15.00 16.50 0.6 9.00 10.00 11.000.7 15.75 17.50 19.25 0.7 10.50 11.67 12.830.8 18.00 20.00 22.00 0.8 12.00 13.33 14.670.9 20
40、.25 22.50 24.75 0.9 13.50 15.00 16.501.0 22.50 25.00 27.50 1.0 15.00 16.67 18.331.1 24.75 27.50 30.25 1.1 16.50 18.33 20.171.2 27.00 30.00 33.00 1.2 18.00 20.00 22.001.3 29.25 32.50 35.75 1.3 19.50 21.67 23.831.4 31.50 35.00 38.50 1.4 21.00 23.33 25.671.5 33.75 37.50 41.25 1.5 22.50 25.00 27.50JEDEC
41、 Standard No, 820APage 72 Operating conditions (contd)Figure 4 Target Pull Down Characteristic at 40 ohmsFigure 5 Target Pull Up/Termination Characteristic at 60 ohms0510152025303540450.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5VmAMin Ideal Max-30-25-20-15-10-500.1 0.2 0.3 0.4 0.5 0.6
42、 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5VmAMin Ideal MaxJEDEC Standard No. 820APage 82 Operating conditions (contd)Figure 6 Example of Nonlinearity, Pull Down Characteristic at 40 ohmsFigure 7 Example of Nonlinearity, Pull Up/Termination Characteristic at 60 ohmsIdeal Non-Linearity0.005.0010.0015.0020.0
43、025.0030.0035.0040.0045.000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5VmAIdeal Non-Linearity-30.00-25.00-20.00-15.00-10.00-5.000.000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5VmAJEDEC Standard No, 820APage 93 Additional Background InformationThe POD I/O system is optimi
44、zed for small systems with data rates exceeding 2.0 Gbps. The system allows a single Master device to control one or two slaves in the case of GDDR5 and one, two or four slave devices in the case of GDDR4. The POD driver uses a 40/60 Ohm output impedance that drives into a 60 Ohm equivalent terminat
45、or tied to VDDQ. Single, dual and quad load systems are shown as follows:Figure 8 System ConfigurationsThe POD Master I/O cell is comprised of a 40/60 Ohm driver and a terminator of 60 Ohms. The Master POD cells terminator is disabled when the output driver is enabled. The basic cell is shown in Fig
46、ure 9.Figure 9 Master I/O CellVDDQ240 Ohm40/60 Ohm240 Ohm 240 Ohm 240 OhmGDDR4 ADD/CMDVDDQ120 Ohm40/60 Ohm120 OhmADD/CMD or GDDR4 Data Bit VDDQ60 Ohm40/60 OhmData Bit or ADD/CMD4 Slaves (GDDR4 only)2 Slaves1 SlaveDQOutput DataOutput EnableVSSQVDDQ60 Ohm TerminatorEnabled when receiving60 Ohm pullup
47、and 40 Ohm pulldownwhen transmittingJEDEC Standard No. 820APage 103 Additional Background Information (contd)The POD Slave I/O cell is comprised of a 40/60 ohm driver and programmable terminator of 60 or 120 ohms for GDDR5 and 60, 120 or 240 ohms for GDDR4. The Slave POD cells terminator is disabled
48、 when the output driver is enabled or any other Slave output driver is enabled. The basic cell is shown in Figure 10.Figure 10 Slave I/O CellThe POD Master and Slave I/O cells are intended to have their driver and terminators combined together to minimize the area needed to implement the cell and re
49、duce input capacitance. For GDDR4 this is possible by using six 240 Ohm driver/terminator sub cells that are connected in parallel. The combinations used are as follows.For GDDR5 this is possible by using three 120 Ohm driver/terminator sub cells that are connected in parallel. The combinations used are as follows.Table 5 POD I/O Sub Cells, 240 Ohm Based# of 240 ohm Sub Cells EnabledResulting Impedance Use
