1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-30SEPTEMBER 2017JEDECSTANDARDPOD125 - 1.25 V Pseudo OpenDrain I/ONOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by t
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9、 www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 8-30Page 1POD125 - 1.25 V PSEUDO OPEN DRAIN I/O(From JEDEC Board Ballot JCB-17-25, formulated under the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard defines the DC and AC single-ended
10、 (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os.The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices.Multiple Classes of POD125 are e
11、xpected to reside within the family of POD125 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD125 are documented in the appendices of this document (e.g., POD125/Class A).The core of this standard documents the subs
12、et of values common to all Classes of POD125 and documents specification items left to definition within a specific Class as denoted by CDV which is defined as Class Dependent Value.The values specific to each particular class of POD125 are found in the annexes. See specific Class tables for further
13、 details.NOTE It does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD125. Multiple Classes may reuse a given specification value if appropriate to the Class requirements.JEDEC Standard No. 8-30Page 22 C
14、ore POD125 Interface StandardTable 1 DC Operating ConditionsParameter SymbolPOD125Unit NotesMin Typ MaxDevice Supply Voltage VDD1.2125 1.25 1.2875 V 1Output Supply Voltage VDDQ1.2125 1.25 1.2875 V 1Reference voltage: DQ and DBI_n pinsReference voltage: CA pinsDC input logic HIGH voltage with VREFC:
15、CADC input logic LOW voltage with VREFC: CADC input logic HIGH voltage with VREFC2: CADC input logic LOW voltage with VREFC2: CADC input logic HIGH voltage with VREFD: DQ, DBI_nDC input logic LOW voltage with VREFD: DQ, DBI_nDC input logic HIGH voltage with VREFD2: DQ, DBI_nDC input logic LOW voltag
16、e with VREFD2: DQ, DBI_nRESET_n and boundary scan input logic HIGH voltage; EDC and CA input logic high voltage for x16/x8 mode, PC vs. 2-channel mode, CK and CA ODT select at resetRESET_n and boundary scan input logic LOW voltage; EDC and CA input logic low voltage for x16/x8 mode, PC vs. 2-channel
17、 mode, CK and CA ODT select at resetInput leakage current (any input 0V = VIN= VDDQ; all other signals not under test = 0V) Output leakage current (outputs are disabled;0V = VOUT= VDDQ)Output logic LOW voltage VOL(DC) 0.52 VSingle ended clock input voltage level: CK_t, CK_c, WCK_t, WCK_cClock input
18、mid-point voltage: CK_t, CK_cClock input differential voltage: CK_t, CK_cClock input differential voltage: WCK_t, WCK_cNOTE 2 DC bandwidth is limited to 20 MHz.NOTE 3 AC noise in the system is estimated at 50mV pk-pk for the purpose of DRAM design.NOTE 4 The reference voltage source and control for
19、DQ and DBI_n pins are determined by Half VREFDand VREFDLevel mode register bits.NOTE 5 Programmable VREFDlevels are not supported with VREFD2.NOTE 6 The reference voltage source (external or internal) is determined at power-up; the reference voltage level is determined by Half VREFCand the VREFCOffs
20、et mode register bits. NOTE 7 Programmable VREFCoffsets are not supported with VREFC2.NOTE 8 VIHRand VILRapply to boundary scan input pins TDI, TMS and TCK. VIHRand VILRapply to EDC and CA inputs at reset when latching default device configurations. VIHRand VILRalso apply to CA, CABI_n, CKE_n, CK, D
21、Q, DBI_n, EDC and WCK inputs when boundary scan mode is active and input data are latched in the Capture-DR TAP controller state.NOTE 9 This provides a minimum of 0.775 V to a maximum of 0.975 V, and is normally 70% of VDDQ. DRAM timings relative to CK_t cannot be guaranteed if these limits are exce
22、eded.NOTE 10 VIDCKis the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input reference level for signals other than CK_t and CK_c is VREFC.NOTE 11 VIDWCKis the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. Th
23、e input reference level for signals other than WCK_t and WCK_c is either VREFC, VREFC2, VREFDor VREFD2.NOTE 12 The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and CK_c cross. Please refer to the applicable timings in the AC Timings table.NO
24、TE 13 Use VIHRand VILRwhen boundary scan mode is active and input data are latched in the Capture-DR TAP controller state.NOTE 14 The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. Please refer to the applicable timings i
25、n the AC Timings table.VREFDCDV CDV V 3, 4VREFD2CDV CDV V 3, 4, 5VREFCCDV CDV V 6VREFC2CDV CDV V 6, 7VIHA(DC) CDV V 8VILA(DC) CDV V 8VIHA2(DC) CDV V 8VILA2(DC) CDV V 8VIHD(DC) CDV V 8VILD(DC) CDV V 8VIHD2(DC) CDV V 8VILD2(DC) CDV V 8VIHRCDV V 8VILRCDV V 8ILAIOZAVIN-0.30 VDDQ+ 0.30 13VMP(DC) VREFC- 0
26、.10 VREFC+ 0.10 V 9, 12VIDCK(DC) CDV V 10, 12VIDWCK(DC) CDV V 11, 14NOTE 1 GDDR6 SGRAMs are designed to tolerate PCB designs with separate VDDand VDDQpower regulators.Table 2 AC Operating Conditions (For Design only11)Parameter SymbolPOD125Unit NotesMin Typ MaxAC input logic HIGH voltage with VREFC:
27、 CAAC input logic LOW voltage with VREFC: CAAC input logic HIGH voltage with VREFC2: CAAC input logic LOW voltage with VREFC2: CAAC input logic HIGH voltage with VREFD: DQ, DBI_nAC input logic LOW voltage with VREFD: DQ, DBI_nAC input logic HIGH voltage with VREFD2: DQ,DBI_nAC input logic LOW voltag
28、e with VREFD2: DQ,DBI_nClock input differential voltage: CK_t, CK_c Clock input differential voltage: WCK_t, WCK_c Clock input crossing point voltage; CK_t, CK_cClock input crossing point voltage: WCK_t, WCK_cAllowed time before ring back of CK/WCK below VIDCK(AC)/VIDWCK(AC)NOTE 2 The value of VIXCK
29、and VIXWCKis expected to equal 70% VDDQfor the transmitting device and must track variations in the DC level of the same.NOTE 3 VIDCKis the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input reference level for signals other than CK_t and CK_c is VREFC
30、.NOTE 4 VIDWCKis the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. The input reference level for signals other than WCK_t and WCK_c is either VREFC, VREFC2, VREFDor VREFD2.NOTE 5 The CK_t and CK_c input reference level (for timing referenced to CK_t and C
31、K_c) is the point at which CK_t and CK_c cross. Please refer to the applicable timings in the AC Timings table.NOTE 6 The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. Please refer to the applicable timings in the AC Tim
32、ings table.NOTE 7 VREFDis either VREFDor VREFD2NOTE 8 Figure 3 illustrates the exact relationship between (CK_t - CK_c) or (WCK_t - WCK_c) and VID(AC), VID(DC) and tDVAC.NOTE 9 Ring back below VID(DC) is not allowed.NOTE 10 tDVACis not measured in and of itself as a compliance specification, but is
33、relied upon in measurement of clock operating conditions and clock related parameters.NOTE 11 The AC Operating conditions are for DRAM design only and are valid on the silicon at the input of the receiver. They are not intended to be measured.JEDEC Standard No. 8-30Page 3VIHA(AC) CDV VVILA(AC) CDV V
34、VIHA2(AC) CDV VVILA2(AC) CDV VVIHD(AC) CDV VVILD(AC) CDV VVIHD2(AC) CDV VVILD2(AC) CDV VVIDCK(AC) CDV V 1, 3, 5VIDWCK(AC)CDV 1, 4, 6VIXCK(AC) VREFC- 0.10 VREFC+ 0.10 V 1, 2, 5VIXWCK(AC)VREFD- 0.09 VREFD+ 0.09 V 1, 2, 6, 7tDVACps 8, 9, 10NOTE 1 For AC operations, all DC clock requirements must be sat
35、isfied as well.JEDEC Standard No. 8-30Page 42 Core POD125 Interface Standard (contd)VIL(AC)VIL(DC)VREF- DC NoiseVREF- DC NoiseVREF+ DC NoiseVREF+ AC NoiseVIH(DC)VIH(AC)VOHVIN(AC) - Provides marginbetween VOL (MAX) andVIL(AC)VDDQVOL (MAX)System Noise Margin (Power/Ground, Crosstalk, Signal Integrity
36、Attenuation)OutputInputNOTE VREF, VIH, VIL refer towhichever VREFxx (VREFD, VREFD2,VREFC, or VREFC2) is being used. Figure 1 Voltage WaveformJEDEC Standard No. 8-30Page 52 Core POD125 Interface Standard (contd)VIX(AC)CK_cCK_tMaximum Clock LevelMinimum Clock LevelVID(AC)VID(DC)VMP(DC)Figure 2 Clock W
37、aveform0VID (AC) MINtDVACtDVAChalf cycletimeDifferential Input Voltage (i.e., WCK_t - WCK_c, CK_t -CK_c)VID (DC) MIN-(VID (DC) MIN)-(VID (AC) MIN)Figure 3 Definition of Differential AC-Swing and “Time above AC-Level” tDVACJEDEC Standard No. 8-30Page 62 Core POD125 Interface Standard (contd)The Drive
38、r and Termination impedances are derived from the following test conditions under worst case process corners:1. Nominal 1.25 V (VDD/VDDQ)2. Power the device and calibrate the output drivers and termination to eliminate process variation at 25 C.3. Reduce temperature to 10 C and recalibrate.4. Reduce
39、 temperature to 0 C and take the fast corner measurement.5. Raise temperature to 75 C and recalibrate6. Raise temperature to 85 C and take the slow corner measurement7. Reiterate 2 to 6 with VDD/VDDQ1.2125 V8. Reiterate 2 to 6 with VDD/VDDQ1.2875 V9. All obtained driver and termination IV characteri
40、stics have to be bounded by the specified MIN and MAX IV characteristics.The following values (ideal with +/- 10% min/max) are targets for the designer and are not required to be met. Vendor datasheets should be consulted for further details. It is expected that the characteristics of the real curve
41、s will have some non-linearity as shown in Figure 6 and Figure 7. This may help to reduce the overall capacitance and boost performance. It is up to the designer to find the optimum combination of lin-earity and capacitance for best RX and TX performance. Table 3 1.25V I/O ImpedancesPull-Down Charac
42、teristic at 40 Ohm Pull-Up/Termination Characteristic at 60 OhmVoltage (V) MIN(mA) Ideal(mA) MAX(mA) Voltage (V) MIN(mA) Ideal(mA) MAX(mA)0.1 2.25 2.50 2.75 0.1 -1.50 -1.67 -1.830.2 4.50 5.00 5.50 0.2 -3.00 -3.33 -3.670.3 6.75 7.50 8.25 0.3 -4.50 -5.00 -5.500.4 9.00 10.00 11.00 0.4 -6.00 -6.67 -7.33
43、0.5 11.25 12.50 13.75 0.5 -7.50 -8.33 -9.170.6 13.50 15.00 16.50 0.6 -9.00 -10.00 -11.000.7 15.75 17.50 19.25 0.7 -10.50 -11.67 -12.830.8 18.00 20.00 22.00 0.8 -12.00 -13.33 -14.670.9 20.25 22.50 24.75 0.9 -13.50 -15.00 -16.501.0 22.50 25.00 27.50 1.0 -15.00 -16.67 -18.331.1 24.75 27.50 30.25 1.1 -1
44、6.50 -18.33 -20.171.2 27.00 30.00 33.00 1.2 -18.00 -20.00 -22.001.25 28.125 31.25 35.375 1.3 -18.75 -21.835 -22.91545403530201510500.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3ideal MaxmAVolts25MinJEDEC Standard No. 8-30Page 72 Core POD125 Interface Standard (contd)Figure 4 Target Pull-Down Ch
45、aracteristic at 40 Ohm0-5-10mAVolts0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3-15-20-25-30idealMin MaxFigure 5 Target Pull-Up/Termination Characteristic at 60 Ohm45.0040.0035.0030.0020.0015.0010.005.000.000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3ideal non-linearitymAVolts25.00JEDEC
46、 Standard No. 8-30Page 82 Core POD125 Interface Standard (contd)Figure 6 Example of Non-Linearity, Pull-Down Characteristic at 40 Ohm0.00-5.00-10.00ideal non-linearitymAVolts0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3-15.00-20.00-25.00-30.00Figure 7 Example of Non-Linearity, Pull-Up/Terminat
47、ion Characteristic at 60 OhmJEDEC Standard No. 8-30Page 93 Additional Background InformationThe POD I/O system is optimized for small systems with very high data rates. The system allows a single master device to control one or two slaves in the case of GDDR6. The POD driver uses either a 60/40 Ohm
48、output impedance that drives into a 60 Ohm equivalent terminator tied to VDDQor a 48/40 Ohm output impedance that drives into a 48 Ohm equivalent terminator tied to VDDQ. Single and dual load systems are shown as follows:VDDQ120 Ohm40/60 Ohm120 OhmCAVDDQ60 Ohm40/60 OhmData Bit or CA2 Slaves1 SlaveFi
49、gure 8 System ConfigurationsThe POD Master I/O cell is comprised of a 60/40 Ohm driver and a terminator of 60 Ohms or a 48/40 Ohm driver and a terminator of 48 Ohms. The Master POD cells terminator is disabled when the output driver is enabled. The basic cell is shown in Figure 9.DQOutput DataOutput EnableVSSVDDQ60 Ohm (or 48 Ohm) TerminatorEnabled when receiving60 Ohm (or 48 Ohm) pull-up and 40 Ohm pull-downwhen transmittingFigure 9 Master I/O CellJEDEC Standard No. 8-30Page 103 Additional Background Information (contd)The POD slave I/O cell is comprise
