1、EIA JESDB-B 96 3234600 0577080 T7T m 00 I EINJEDEC STANDARD Stub Series Terminated Logic for 3.3 Volts (SSTL EIAIJESDS-S AUGUST 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT NOTICE EWJEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and
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7、stions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 l. Published by (SELECTRONIC INDUSTRIES ASSOCIATION 1996 Engineering Department 2500 Wilson Boulevard Arlington,
8、VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are fiee to duplicate this document in amrdance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and ProCsdure“. PRICE: Please refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEE
9、RING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EIA JESD8-8 96 m 3234600 0577082 862 m JEDEC Standard No. 8-8 Stub Series Terminated Logic for 3.3 Volts (SSTL-3) Contents Page 1. Scope 1 1.1 St
10、andard Structure 1 1.2 Rational and Assumptions 1 2 Supply Voltage and logic input Levels 3 2.1 Supply Voltage Levels 4 2.2 Input Parametrics 4 2.3 AC Test Conditions 5 3 SSTL-3 Output Buffers 6 3.1 SSTL-3 Class I Output Buffers 8 3. l. 1 Push-pull Output Buffers 8 3.12 STTL-3 Class I Output ac Test
11、 Conditions 9 3.2 SSTL-3 Class II Output Buffers 10 3.2.1 Push-pull Output Buffers 10 3.22 STTL-3 Class II Output ac Test Conditions 11 3.3 Other Applications 12 3.3.1 Push-pull Output Buffer Unterminated Load 12 3.3.2 Push-pull Output Buffer Terminated load 12 3.3.3 Push-Pull Output Buffer External
12、 Source 13 3.3.4 Push-pull Output Buffer for Symmetric Double Parallel Terminated Load 14 -1- EIA JESD8-8 96 m 3234600 0577083 7T9 m JEDEC Standard No. 8-8 Intentionally le Blank -u- JEDEC STANDARD NO. 8-8 Page 1 Stub Series Terminated Logic for 3.3 Volts (SSTL - 3) A 3.3 V Supply Voltage based inte
13、rface standard for digital integrated circuits (From JEDEC Council Ballot JCB-96-23, formulated under the cognizance of the JC-16 Committee on Electrical Interface and Power Supply Standards for Digital Integrated Circuit Components.) 1 Scope This standard defines the input, output specifications an
14、d ac test conditions for devices that are designed to operate in the SSTL-3 logic switching range, nominally O V to 3.3V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. In many cases VDD and VDDQ will have the same voltage level. However for noise rejection
15、reasons, the sup- plies may be routed separately in the system interconnect. The VDD value is not specified in this standard other than that VDDQ value may not exceed that of VDD. 1.1 Standard structure The standard is defined in three sections: The first section defines pertinent supply voltage req
16、uirements common to all compliant ICs. The second section defines the minimum dc and ac input parametric requirements and ac test con- ditions for inputs on compliant devices. The third section specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs ta
17、rgeted for various application environments. The output specifications are divided into two classes, Class I and Class II, which are distinguished by drive requirements and application. A given IC need not be equipped with both classes of output drivers, but each must support at least one to claim S
18、STL-3 output compliance. The full input reference level (VREF) range specified is required on each IC in order to allow any SSTL-3, IC to receive signals from any SSTL-3 output driver. 1.2 Rationale and assumptions The SSTL-3 standard has been developed particularly with the objective of providing a
19、 relatively JEDEC STANDARD NO. 8-8 Page 2 simple upgrade path from LVTTL designs. The standard is particularly intended to improve Oper- ation in situations where busses must be isolated from relatively large stubs. External resistors provide this isolation and also reduce the on-chip power dissipat
20、ion of the drivers. Busses may be terminated by resistors to an external termination voltage. Actual selection of the resistor values is a system design decision and beyond the scope of this standard. However in order to provide a basis, the driver characteristics will be derived in terms of a typic
21、al 50 Ohms environment. While driver characteristics are derived from a 50 Ohm environment, this standard will work for other impedance levels. The system designer will be able to vary impedance levels, termination resistors and supply voltage and be able to calculate the effect on system voltage ma
22、rgins. This is accomplished precisely because drivers and receivers are specified independently of each other. The standard defines a reference voltage VREF which is used at the receivers as well as a voltage VTT to which termination resistors are connected. In typical applications VTT tracks as a r
23、atio of VDDQ. In turn VREF will be given the value of VTT. In some standards this ratio equals 0.5. If this value were to be applied to SSTL-3, the maximum value of VTT and thus VREF would be 1.8 V (0.5 * 3.6). In order to be more closely compatible with LVTTL, the nominal ratio was selected to be 0
24、.45. This leads to a typical VTT and VREF value of about 1.5 V if VDDQ = 3.3 V. This value is close to the internal reference voltage in current LVTTL designs. EIA JESDB-B 96 m 3234600 0577086 408 m JEDEC STANDARD NO. 8-8 Page 3 2 Supply voltage and logic input levels The standard defines both ac an
25、d dc input signal values. Making this distinction is important for the design of high gain, differential, receivers that are required. The ac values are chosen to indi- cate the levels at which the receiver must meet its timing specifications. The dc values are chosen such that the final logic state
26、 is unambiguously defined, that is once the receiver input has crossed this value, the receiver will change to and maintain the new logic state. The reason for this approach is that many input waveforms will include a certain amount of “ringing”. The system designer can be sure that the device will
27、switch state a certain amount of time after the input has crossed ac threshold and not switch back as long as the input stays beyond the dc threshold. The relationship of the different levels is shown in figure 2. l. An example of ringing is illustrated in the dotted waveform. Il VDDQ ” -” VIH(ac) V
28、IH(dc) VREF ”_”_ - - - - - - - - ”“” - - - - - - - - VIL(dc) VIL(ac) “” ”_ ”_ vss Figure 2.1 - SSTL-3 Input levels JEDEC STANDARD NO. 8-8 Page 4 2.1 Supply voltage levels II Table 2.1 - Supply voltage levels Parameter VREF + 0.05 VREF VREF - 0.05 Termination voltage 1.7 1.5 1.3 Input reference volta
29、ge 3.6 3.3 3 .O Output supply voltage da VDDQ Device supply voltage Max. Nom Min. Units 1 V Notes V 293 V 1 4 V Notes: 1. There is no specific device VDD supply voltage requirement for SSTL-3 compliance. However under all 2. The value of VREF may be selected by the user to provide optimum noise marg
30、in in the system. Typi- conditions VDDQ must be less than or equal to VDD. cally the value of VREF is expected to be about 0.45 * VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 3. Peak to peak ac noise on VREF may not exceed 2% VREF (dc). 4. VTT of transmitting dev
31、ice must track VREF of receiving device. 2.2 Input parametric Table 2.2-a - Input dc logic levels Symbol 1 V VREF - 0.20 - 0.30 dc input logic low VIL (dc) 1 V VDDQ + 0.3 VREF + 0.20 dc input logic high VIH (dc) Notes Units Max. Min. Parameter Notes: l. Within this standard, it is the relationship o
32、f the VDDQ of the driving device and the VREF of the receiv- ing device that determines noise margins. However, in the case of VIH (Max.) (Le. input overdrive) it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented that sup ports SSTL-3 inputs but has no
33、 SSTL-3 outputs (e.g., a translator), and therefore no VDDQ supply volt- age connection, inputs must tolerate input overdrive to 3.9 V (High comer VDDQ + 300 mV). Table 2.2-b - Input ac logic levels - Symbol VIH (ac) Notes Units Max. Min. Parameter V VEF -0.40 ac input logic low Vu, (ac) V VREF 0.40
34、 ac input logic high JEDEC STANDARD NO. 8-8 Page 5 2.3 AC Test Conditions The ac input test conditions are specified to be able to obtain reliable, reproducible test results in an autonated test environment, where a relatively high noise environment makes it difficult to create clean signals with li
35、mited swing. The tester may therefore supply signals with a 2 V peak to peak swing to drive the receiving device. Note however, that all timing specifications are still set relative to the ac input level. This is illustrated in figure 2.3. Table 2.3 ac input test conditions Symbol Notes Units Value
36、Condition VFEF 3 V/ ns 1 .o Input signal minimum slew rate SLEW 132 V 2.0 Input signal maximum peak to peak swing VSWINGmax 1,4 V 0.45 * VDDQ Input reference voltage Notes: l. In all cases, input waveform timing is referenced to the input signal crossing through the VF level 2. Compliant devices mus
37、t still meet the VIH(ac) and VIL(ac) specifications under actual use conditions. 3. The 1V/ns input signal minimum slew rate is to be maintained in the VILmax(ac) to VIHmin(ac) range of the input signal swing, consistent with the ac logic specification of table 2.2-b. See also figure 2.3. 4.It was a
38、greed in JEDEC discussions that ac test conditions could be measured under nominal voltage con- ditions as long as the supplier can demonstrate by analysis that that the device will meet its timing speci- fications under all supported voltage conditions. applied to the device under test. Table 2.1 i
39、dentifies the VF range supported in SSTL-3. VDDQ ”“” -”“” “” - VIHmin (ac) VSWING(max) I i ” t-:”*”-t-+ ”_ -VILmax(ac) “” 1 I I I vss I deltaTt deltaT I I I SLEW= (VIHmin(ac) - VILmax(ac) / deltaT Figure 2.3 AC Input Test Signal Waveform EIA JESD8-8 96 I 3234600 0577089 117 W JEDEC STANDARD NO. 8-8
40、Page 6 3 SSTL - 3 Output Buffers 3.0 Overview This specification sets minimum requirements for output buffers in such a way that when they are applied within the range of power supply voltages specified in SSTL-3 and are used in conjunc- tion with SSTL-3 input receivers then the input receiver speci
41、fications can be met or exceeded. The specifications are quite different from traditional specifications, where minimum values for VOH and maximum values for VOL are set which apply to the entire supply range. In SSTL-3, the input voltage provided to the receiver depends on the driver as well as on
42、the termination volt- age and termination resistors. Figure 3.0 shows the typical dc environment that the output buffer is presented with. Output Buffer VTT (Driver) I Receiver VDDQ / / I vom VIN vss Figure 3.0 Typical Output Buffer (Driver) environment Of particular interest here are the values VOU
43、T and VIN. These values depend not only on the current drive capabilities of the buffer, but also on the values of VDDQ and VTT (VREF is equal to VTT). The important condition is that VIN be at least 400mV above or below VREF as a result of VOUT attaining its maximum low or its minimum high value. A
44、s will be seen later, the two cases of interest for SSTL-3 are where the series resistor RS equals 25 Ohms and the termination resistor RT equals 50 Ohms (for Class I) or 25 Ohms (for Class II). VTT is specified as being equal to 0.45 * VDDQ. In order to meet the 400mV minimum requirement for Vin, a
45、 minimum of 8mA must be devel- oped across RT if RT equals 50 Ohms (Class I) or 16mA in case RT equals 25 Ohms (Class II). The driver specification now must guarantee that these values of VIN are obtained in the worst case conditions specified by this standard. EIA JESDB-8 96 3234b00 0577090 939 JED
46、EC STANDARD NO. 8-8 Page 7 Table 3.0 Spread sheet showing SSTL-3 circuit voltages depending on VDDQ. (For reference only) Conditions Class II Class II Class II Class I Class I Class I Units VDDQ 3.6 3.3 3.0 3.6 3.3 3 .O V VTT 1.7 1.5 1.3 1.7 1.5 1.3 V VREF 1.7 1.5 1.3 1.7 1.5 1.3 V I On resistance I
47、 Ohms I 87.50 I 112.50 I 137.50 I 31.25 I 43.75 I 56.25 1 As can be seen from Table 3.0 the most stringent requirements will result where VDDQ= 3.0 V, since for that case the output driver transistors must have the lowest “on“ resistance. If the driver outputs are sized for this condition, then for
48、all other VDDQ voltage applications, the resulting input signal will be larger than the minimum required 400mV. JEDEC STANDARD NO. 8-8 Page 8 3.1 SSTL-3 Class I output buffers 3.1.1 Push-pull output buffer for symmetrically parallel terminated loads with series resis- tor. (VTT = 0.45 * VDDQ) Table
49、3.1-a - Output dc current drives I Symbol I Parameter Min. Max. I Units I Notes II I IOH (dc) 2,394 mA 8 Output minimum sink dc current IOL (dc) 1,394 mA -8 Output minimum source dc current Notes: 2. VDDQ = 3.0 V; VOUT = 0.7 V. 3. The dc value of VREF applied to the receiving device is expected to be set to VTT. 4. The values of IOH(dc) and IOL(dc) are based on VDDQ = 3.0 V and VTT = 1.3 V. They are used to test device current drive capability which ultimately delivers acceptable noise margin for an SSTL-3 receiver. Under these conditions VOH is 1.9 V
