1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-12AAPRIL 2007JEDECSTANDARDDefinition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications(Revision of JESD82-12, November 2004) NOTICE JEDEC standards and publications contain material that has been prepared, review
2、ed, and approvedthrough the JEDEC Council level and subsequently reviewed and approved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and
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5、d publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestio
6、ns relative to the content of this JEDEC standard or publicationshould be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington,
7、 VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Public
8、ations at www.jedec.org Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies throu
9、gh entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-12APage 1DEFINITION OF THE SSTU32S869 AND SSTU32D869 REGISTERED BUFFER FOR DDR2 WITH PARITY RDIMM
10、 APPLICATIONS(From JEDEC Board Ballot JCB-04-97 and JCB-07-05, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D
11、869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.The purpose is to provide a standard for the SSTU32S869 and SSTU32D869 (see Note) logic devices, for uniformity, multiplicity of sources, eliminatio
12、n of confusion, ease of device specification, and ease of use.NOTE The designations SSTU32S869 and SSTU32D869 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a com
13、plete part designation.2 Device standard2.1 DescriptionThis 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDDoperation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized t
14、o drive the DDR2 DIMM load, following the SSTL_18 standard. They provide 50% more dynamic driver strength than the standard SSTU32864 outputs. The SSTU32S869 and SSTU32D869 operate from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.The devic
15、e supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are f
16、orced low. The LVCMOS RESET input must always be held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.In the DDR2 RDIMM application, RESET is specified to be completely asynchr
17、onous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the
18、 register will become active quickly, relative to the time to enable the differential input receivers. SSTU32S869 and SSTU32D869 must ensure that the outputs remain low as long as the data inputs are low, the clock is stable during the time from the low-to-high transition of RESET and the input rece
19、ivers are fully enabled. This will ensures that there are no glitches on the output. JEDEC Standard No. 82-12APage 22 Device standard (contd)2.1 Description (contd)If the data inputs are not held low, then DCS and CSR must be held high, DODT and DCKE must be held low, and all other inputs must remai
20、n stable (either low or high) for a minimum of tACT(max) after the rising edge of RESET.The parity error output PTYERR will be reset to high by RESET transitioning low and will not be decoded until after RESET goes high and DCS and/or CSR are asserted low.The device monitors both DCS and CSR inputs
21、and will gate the Qn, PPO (Paritial-Parity-Out) and PTYERR (Parity Error) Parity outputs from changing states when both DCS and CSR are high. If either DCS or CSR input is low, the Qn, PPO and PTYERR outputs will function normally. The RESET input has priority over the DCS and CSR controls and will
22、force the Qn and PPO outputs low and the PTYERR high. The SSTU32S869 and SSTU32D869 include a parity checking function. The SSTU32S869 and SSTU32D869 accept a parity bit from the memory controller at its input pin PARIN one or two cycles after the corresponding data input, compares it with the data
23、received on the D-inputs and indicates on its open-drain PTYERR pin (active low) whether a parity error has occurred. The number of cycles depends on the setting of C1/C2, see Figure 6 and 7.When used as a single device, the C1/C2 inputs are tied low. When used in pairs, the C1/C2 inputs are tied lo
24、w for the first register (front) and the C1/C2 inputs are tied high for the second register. When used as a single register, the PPO and PTYERR signals are produced two clock cycles after the corresponding data input. When used in pairs, the PTYERR signals of the first register are left floating. Th
25、e PPO outputs of the first register are cascaded to the PARIN signals on the second register (back). The PPO and PTYERR signals of the second register are produced three clock cycles after the corresponding data input. Parity implementation and device wiring for single and dual die is described in F
26、igure 1.If an error occurs, and the PTYERR is driven low, it stays low for two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, CSR and DODT) are not included in the parity check computations.All registers used on an individual DIMM must be of the same configuration,
27、 i.e single or dual die.JEDEC Standard No. 82-12APage 32 Device standard (contd)2.1 Description (contd)Figure 1 Parity implementation and device wiring for SSTU32S869 and SSTU32D869 PTYERR1 W1Register 1(Front)Parin1, W4NC, A8ParinSSTU32S869 (1)PPO1, W8 Parin1, W4NC, A4Register 2(Back)NC, A8NC, A11Se
28、t C1 = 0 for Register 1; Set C1 = 1 for Register 2. NC denotes No ConnectPTYERR1 W1Register 1(Front)Parin1, W4Parin2, A8ParinSSTU32D869PPO1, W8 Parin1, W4PPO2, A4Register 2(Back)Parin2, A8PTYERR2, A11Set C1 and C2 = 0 for Register 1; Set C1 and C2 = 1 for Register 2.JEDEC Standard No. 82-12APage 42
29、Device standard (contd)Package options include 150-ball Thin Profile Fine Pitch BGA (TFBGA) (11 19 array, 8.0 13.0 mm body size, 0.65 mm pitch, MO-225, Variation TBD).2.2 150-ball TFBGA (MO-225xx)Figure 2 Pinout configuration1(TOP VIEW)23456789101ABCDEFGHJKLMNPRTUVWJEDEC Standard No. 82-12APage 52 D
30、evice standard (contd)2.3 Pinout top view for 150-ball TFBGA150-ball, 11 19 grid, TOP VIEWNB indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die).Figure 3 Pinout top view for 150-ball TFBGANOTE 1 MCL denotes input pin that must be conn
31、ected Low. Register Vendors: Implement NC or input on Ball A3, A9, W3, W9 NOTE 2 NC for single die version123456789101ANB VDDMCL(1)PP02(2)GND VREF GNDPARIN2(2)MCL(1)VDDPTYERR2(2)BVDD NB VDD GND GND GND GND GND VDD NB VDDCQCKEA VDD NB GND NB GND NB GND NB VDD QCKEBDQ2A VDD GND NB DCKE NB D2 NB GND VD
32、D Q2BEQ3A VDD NB D3 NB NC NB DODT NBC2(2)Q3BFQODTA VDD GND NB NC NB NC NB GND VDD QODTBGQ5A VDD GND D5 NB CLK NB D6 GND VDD Q5BHQ6A NB GND NB NC NB NC NB GND NB Q6BJQCSA VDD NB NC NB RESET NB CSR NB VDD QCSBKVDD VDD GND GND NB NB NB GND VDD VDD VDDLQ8A VDD NB DCS NB CLK NB D8 NB VDD Q8BMQ9A NB GND N
33、B NC NB NC NB GND NB Q9BNQ10A VDD GND D9 NB NC NB D10 GND VDD Q10BPQ11A VDD GND NB NC NB NC NB GND VDD Q11BRQ12A C1 NB D11 NB NC NB D12 NB VDD Q12BTQ13A VDD GND NB D13 NB D14 NB GND VDD Q13BUQ14A VDD NB GND NB GND NB GND NB VDD Q14BVVDD NB VDD GND GND GND GND GND VDD NB VDDWPTYERR1 VDDMCL(1)PARIN1 G
34、ND VREF GND PPO1MCL(1)VDD NBJEDEC Standard No. 82-12APage 62 Device standard (contd)2.4 Terminal functionsNOTE 1 Inputs D1, D4 and D7 and their corresponding outputs Qn are not included in this range. NOTE 2 NC for single die version. Table 1 Terminal functionsSignal Group Signal Name Type Descripti
35、onUngated inputs DCKE, DODT SSTL_18 DRAM function pins not associated with Chip Select.Chip Select gated inputsD1 . D14(1)SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW.Chip Select inputsDCS, CSR SSTL_18 DRAM Chip Select signals. This pins initiate DRAM address/command decodes, and as s
36、uch at least one will be low when a valid address/command is present. Re-driven outputsQ1A.Q14A, Q1B . Q14B, QCSA ,QCSB QCKEA,QCKEB QODTA,QODTBSSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.Parity input PARIN1, PARIN2(2)SST
37、L_18 Input parity is received on pin PARIN and should maintain parity across the D1.D14(1)inputs, at the rising edge of the clock, one clock cycle after Chip Select is LOW.Parity outputPPO1, PPO2(2)SSTL_18Partial Parity Output. Indicates parity out of D1-D14(1)Parity error outputPTYERR1,PTYERR2(2)Op
38、en drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by in total 2 clock cycles for compatibility with final parity out timing on the industry-standard DDR2 register with
39、 parity (in JEDEC definition).Configuration InputsC1, C2 1.8V LVCMOSWhen Low, register is configured as Register 1. When High, register is configured as Register 2. Clock inputs CK, CK SSTL_18 Differential master clock input pair to the register. The register operation is triggered by a rising edge
40、on the positive clock input (CK).Miscellaneous inputsRESET 1.8 V LVCMOSAsynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal.VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (inte
41、rnally tied together) are used for increased reliability.VDD Power Input Power supply voltageGND Ground Input GroundJEDEC Standard No. 82-12APage 72 Device standard (contd)2.5 Function tableTable 2 Function table (each flip flop)Inputs OutputsRESET DCS CSR CK CKDn, DODT, DCKEQn QCSQODT, QCKEHLLLLLLH
42、LLHHLHH L L L or H L or H XQ0Q0Q0HLHLLLLHLHHHLHH L H L or H L or H XQ0Q0Q0HHLLLHLHHLHHHHH H L L or H L or H XQ0Q0Q0HHHLQ0HLHHHHQ0HHH H H L or H L or H XQ0Q0Q0LX or floatingX or floatingX or floatingX or floatingX or floatingLLLJEDEC Standard No. 82-12APage 82 Device standard (contd)2.5 Function tabl
43、e (contd)Table 3 Parity and Standby function tableNOTE 1 Inputs D1, D4 and D7 are not included in this range.NOTE 2 PARIN1 and PARIN2 arrives one (C1, C2 =0) or two (C1, C2=1) clock cycles after data to which it applies.NOTE 3 This transition assumes PTYERR is high at the crossing of CK going high a
44、nd CK going low. If PYTERR is low, it stays latched low for two clock cycles or until RESET is driven low. PARIN1 is used to generate PPO1 and PTYERR1. PARIN2 is used to generate PPO2 and PTYERR2.NOTE 4 PARIN2, PPO2 and PTYERR2 not required for single die.Inputs OutputRESET DCS CSR CK CK of inputs =
45、 HD1.D14(1)PARIN1(2),PARIN2(4)PPO1(2),PPO2(4)PTYERR1(3)PTYERR2HLX EvenLL HHLX OddLH LHLX EvenHH LHLX OddHL HHLL EvenLL HHLL OddLH LHLL EvenHH LHLL OddHL HHHHXXPPOn0PTYERRn0HX X L or H L or H XXPPOn0PTYERRn0LX or floatingX or floatingX or floatingX or floatingX or floating X or floating L HJEDEC Stan
46、dard No. 82-12APage 92 Device standard (contd)2.6 Logic diagramFigure 4 Logic diagram (positive logic)CKDODTDRDRDCSDRDRDRPARIN1,PARIN2DRDCKEVREFD1D14LSP0 internal node (CS Active)QODTAQODTBQCSAQCSBQCKEAQCKEBQ14AQ14BQ1AQ1B11RESETCKCSRPARITYGENERATORANDCHECKER222PTYERR1,PTYERR2PPO1,PPO2JEDEC Standard
47、No. 82-12APage 102 Device standard (contd)2.7 Register timingNOTE 2 PARIN1 is used to generate PPO1 and PTYERR1. PARIN2 is used in the dual die version to generate PPO2 and PTYERR2. PARIN2, PPO2 and PTYERR2 are not present in single die versions.Figure 5 Timing of clock, data and parity signals. JED
48、EC Standard No. 82-12APage 112 Device standard (contd)2.7 Register Timing (contd)Figure 6 Timing Diagram for the 1st SSTU32S869 and SSTU32D869 C1/C2=0Note 1 This range doesnt include D1, D4 and D7 and their corresponding outputsNote 2 PARIN1 is used to generate PPO1 and PTYERR1. In SSTU32D869 PARIN2
49、 is used to generate PPO2 and PTYERR2JEDEC Standard No. 82-12APage 122 Device standard (contd)2.7 Register Timing (contd)Figure 7 Timing Diagram for the 2nd SSTU32S869 and SSTU32D869, C1/C2=1Note 1 This range doesnt include D1, D4 and D7 and their corresponding outputsNote 2 PARIN1 is used to generate PPO1 and PTYERR1. In SSTU32D869 PARIN2 is used to generate PPO2 and PTYERR2JEDEC Standard No. 82-12APage 132 Device standard (contd)2.7 Register Timing (contd)Figure 8 Timing diagram
