1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-15NOVEMBER 2005JEDECSTANDARDStandard for Definition of CUA878 PLLClock Driver for Registered DDR2 DIMM ApplicationsNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directo
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9、ssociation 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-15Page 1STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVERFOR REGISTERED DDR2 DIMM APPLICATIONS(Formerly JEDEC Board Ballot JCB-05-90, formulated under the cognizance of the JC-40 Committee o
10、n Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA878 PLL clock device, for uniformit
11、y, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Definitions for the purpose of this documentCI() Delta input capacitance.t(su) Sum of the Setup-time skew parameters.t(h) Sum of the Hold-time skew parameters.3 Device standard3.1 DescriptionThis P
12、LL Clock Buffer is designed for a VDDQ of 1.8 V, an AVDDof 1.8 V and differential data input and output lev-els. Package options include a plastic 52-ball VFBGA and a 40-pin VFQFPN.The device is a zero delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pair of
13、 clock outputs (Y0:9, Y0:9) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FBOUT/FBOUT) are di
14、sabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on Y7/Y7 (they are free running in addition to FBOUT/FBOUT). When
15、AVDDis grounded, the PLL is turned off and bypassed for test purposes.When both clock signals (CK, CK) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a
16、 low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FBIN, F
17、BIN) and the input clock pair (CK, CK) within the specified stabilization time tL.The PLL in the CUA878 clock driver uses the input clocks (CK, CK) and the feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y0:9, Y0:9). The CUA878 is also able
18、to track Spread Spectrum Clocking (SSC) for reduced EMI.The CUA878 is characterized for operation from 0oC to 70 oC.JEDEC Standard No. 82-15Page 23 Device standard (contd)3.1 Description (contd)TopviewFigure 1 52-Ball VF-BGA (10x6 Array, 7.0x4.5 mm Body Size, 0.65 mm Pitch, MO-225 Variation BA) pack
19、age pinoutsFigure 2 40-pin HP-VFQFP-N (6.0x6.0 mm Body Size, 0.5 mm Pitch, MO-220, variation VJJD-2, E2 & D2 nominal = 2.9 mm +/- 0.15 mm) package pinoutsGND GND GND Y6Y2 GND NB NB GND Y7Y2 VDDQ VDDQ OS Y7CK NB NB FbinVDDQ NB NB OE FbinVDDQ VDDQ VDDQ VDDQ FboutAVDD GND GND FboutGND GNDY1VDDQVDDQCKAG
20、NDGNDY3NBNBY8Y6Y1 Y0 Y5 Y5Y0612 453CDEHBFGJAY3K Y4 Y9 Y9 Y8Y4BGAVDDQGNDGNDMLFVDDQ1234567891011 12 13 14 15 16 17 18 19 202122232440 39 38 37 36 35 34 33 32 31302928272625 FBOUTVDDQFBINFBINY7Y9 Y8 Y8FBOUTY7Y6Y6Y1VDDQY9VDDQGNDY5Y5Y0 Y0AVDDVDDQAGNDCKY2Y2Y3Y3 Y4Y4CKVDDQVDDQOSOEY1GNDVDDQVDDQJEDEC Standar
21、d No. 82-15Page 33.2 Terminal functions3.3 Function table* L(Z)means the outputs are disabled to a low state meeting the IODLlimit in Table 5.Table 1 Terminal FunctionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground GroundAVDDAnalog power 1.8 V nominalCK Clock input with a (10K-10
22、0K Ohm) pulldown resistor Differential inputCK Complementary clock input with a (10K-100K Ohm) pulldown resistor Differential inputFBIN Feedback clock input Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential outputFBOUT Complementary
23、feedback clock output Differential outputOE Output Enable (Asynch) LVCMOS inputOSOutput Select (tied to GND or VDDQ)LVCMOS inputGND Ground GroundVDDQLogic and output power 1.8 V nominalY0:9 Clock outputs Differential outputsY0:9 Complementary clock outputs Differential outputsNB No ballTable 2 Funct
24、ion tableInputs OutputsPLLAVDDOE OS CK CK YYFBOUT FBOUTGND H X L H L LHBypassed/OffGND H X H L HL LBypassed/OffGND L H L H*L(Z)*L(Z) LHBypassed/OffGND L L H L*L(Z),Y7 active*L(Z),Y7 activeHLBypassed/Off1.8V(nom) LHLH*L(Z)*L(Z) LHOn1.8V(nom) LLHL*L(Z),Y7 active*L(Z),Y7 activeHL On1.8V(nom) HXLHLHLHOn
25、1.8V(nom) H X H L HLHL On1.8V(nom) XXLL*L(Z)*L(Z)*L(Z)*L(Z)Off1.8V(nom) HH ResrvedJEDEC Standard No. 82-15Page 43.4 Logic diagramFigure 3 Logic diagram (positive logic)Y8Y8Y7Y7Y6Y6Y5Y5Y4Y4Y3Y3Y2Y2Y1Y1Y0Y0Y9Y9FBOUTFBOUTPowerdownControl andTest LogicAVDDCKFBINCKFBINPLLOELD* or OEPLL bypassLD*LD*, OS o
26、r OEOS* The Logic Detect (LD) powers down the device when alogic low is applied to both CK and CK.GND10K-100kJEDEC Standard No. 82-15Page 53.5 Absolute maximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage range, VDDQor AVDD. . . . . . .
27、 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 2.5 VInput voltage range, VI(see Notes 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VOutput voltage range, VO(see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . .
28、 . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAOutput clamp current, IOK(VOVDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output curren
29、t, IO(VO= 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous current through each VDDQor GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . .
30、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions bey
31、ond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2 The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 3
32、 This value is limited to 2.5 V maximum.3.6 Recommended operating conditionsNOTE 1 The PLL is turned off and bypassed for test purposes when AVDDis grounded. During this test mode, VDDQremains within the recommended operationing conditions and no timing parameters are guaranteed.NOTE 2 VIDis the mag
33、nitude of the difference between the input level on CK and the input level on CK, see Figure 12 for definition. For CK and CK the VIHand VILlimits are used to define the DC low and high levels for the logic detect state. Table 4 Recommended operating conditions (see Note 1)Min Nom Max UnitVDDQOutput
34、 supply voltage 1.7 1.8 1.9 VAVDDSupply voltage, see Note 1VDDQVILLow-level input voltage, see Note 2OE, OS, CK, CK0.35 x VDDQVVIHHigh-level input voltage, see Note 2OE, OS, CK, CK0.65 x VDDQVIOHHigh-level output current, see Figure 5 9 mAIOLLow-level output current, see Figure 5 9 mAVIXInput differ
35、ential-pair cross voltage(VDDQ/2)-0.15 (VDDQ/2)+0.15VVINInput voltage level 0.3VDDQ+ 0.3VVIDInput differential voltage,see Note 2 and Figure 12DC 0.3VDDQ+ 0.4VAC 0.6VDDQ+ 0.4VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82-15Page 63.7 DC specificationsNOTE 1 Total IDD= IDDQ+IADD= FCK* C
36、PD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequency, VDDQis the power supply and CPDis the Power Dissipation Capacitance.Table 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inp
37、uts II= 18 mA1.7 V 1.2 VVOHHigh output voltageIOH= 100 A1.7 to 1.9 VVDDQ-0.2VIOH= 9 mA1.7 V 1.1VOLLow output voltageIOL= 100 A1.7 to 1.9 V 0.1VIOL= 9 mA1.7 V 0.6IODLOutput disabled low currentOE = L, VODL= 100mV1.7 V 100 AVODOutput differential voltage, the magnitude of the difference between the tr
38、ue and complimentary outputs, see Figure 12 for definition.1.7 V 0.6 VIICK, CKVI= VDDQor GND1.9 V 250AOE, OS, FBIN, FBINVI= VDDQor GND1.9 V 10IDDLDStatic supply current, IDDQ+ IADDCK and CK = L 1.9 V 500 AIDDDynamic supply current,IDDQ+ IADD, see Note 1 for CPDcalculationCK and CK = 410 MHz,all outp
39、uts are open (not connected to a PCB)1.9 V 300 mACICK and CKVI= VDDQor GND1.8 V23pFFBIN and FBIN VI= VDDQor GNDCI()CK and CK VI= VDDQor GND0.25FBIN and FBIN VI= VDDQor GND0.25JEDEC Standard No. 82-15Page 73.8 Timing requirementsNOTE 1 The PLL must be able to handle spread spectrum induced skew.NOTE
40、2 Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)NOTE 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters.NOTE 4
41、 Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t(), after power-up. During normal operation, the stabilization time is also the time required for the
42、 integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Table 6 Tim
43、ing requirements over recommended operating free-air temperature range.AVDD, VDDQ= 1.8 V 0.1 VUNITMIN MAXfCKOperating clock frequency (see Notes 1 and 2) 125 410 MHzApplication clock frequency (see Notes 1 and 3) 160 410 MHztDCInput clock duty cycle 40 60 %tLStabilization time (see Notes 4) 6 sJEDEC
44、 Standard No. 82-15Page 83.9 AC specificationsTable 7 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted) (see Note 6)NOTE 1 Static Phase Offset does not include Jitter.NOTE 2 Period Jitter and Half-Period Jitter specifications are separate specifi
45、cations that must be met independently of each other.DESCRIPTION DIAGRAMfCK(MHz)AVDD, VDDQ= 1.8 V 0.1 VUNITMIN Nom MAXtenOE to any Y/Y see Figure 14 160 to 410 8 nstdisOE to any Y/Y see Figure 14 160 to 410 8 nsslr(i)Output Enable (OE) see Figure 12 160 to 410 0.5 V/nsInput clock slew rate, measured
46、 single ended.see Figure 12 160 to 410 1 2.5 4 V/nsslr(o)Output clock slew rate, measured single ended. (see Notes 3, 5)see Figures 4 and 12160 to 410 1.5 2.5 3 V/nsVOXOutput differential-pair cross- voltage, (see Note 4)see Figure 5 160 to 410(VDDQ/2) - 0.1(VDDQ/2) + 0.1Vtjit(cc+)Cycle-to-cycle per
47、iod jitter see Figure 7 160 to 410040pstjit(cc-) 0 40 pst()Static phase offset (see Note 1)see Figure 8 160 to 410 50 50 pst()dynDynamic phase offset(see Note 7)see Figure 13160 to 270 50 50 ps271 to 410t()dyn(min)t()dyn(max)pstsk(o)Output clock skew(see Note 7)see Figure 9160 to 270 40 ps271 to 410
48、tsk(o)maxpstjit(per)Period jitter(see Notes 2, 7)see Figure 10160 to 270 40 40 ps271 to 410tjit(per)mintjit(per)maxpstjit(hper)Half-period jitter(see Note 2)see Figure 11160 to 270 75 75 ps271 to 410 50 50 pst(su)|tjit(per)| + |t()dyn| + tsk(o)(see Note 7)271 to 410 80 pst(h)|t()dyn| + tsk(o)(see No
49、te 7)271 to 410 60 psThe PLL in the CUA878 must be capable of meeting all the above test parameters while supporting SSC synthesizers with the following parameters: SSC modulation frequency 30.00 33 kHzSSC clock input frequency deviation0.00 0.50 %CUA878 PLL designs should target the values below to minimize the SSC induced skew:PLL Loop bandwidth (-3 dB from unity gain)2.0 MHzJEDEC Standard No. 82-15Page 93.9 AC Specifications (cont.)NOTE 3 The Output Slew Rate is determined from the IBIS model int
