1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD82-18AJANUARY 2007JEDECSTANDARDStandard for Definition of CUA877 and CU2A877 PLL Clock Drivers for for Registered DDR2 DIMMApplications (Revison of JESD82-18, May 2006)NOTICE JEDEC standards and publications contain material that has been prepared, reviewe
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6、ents, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may b
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9、es through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 82-18APage 1STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERSFOR REGISTERE
10、D DDR2 DIMM APPLICATIONS(From JEDEC Board Ballots JCB-05-91 and JCB-06-66, formulated under the cognizance of the JC-40 Committee on Digital Logic.)1 ScopeThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and
11、 CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. 2 Definitions for the purpose of this
12、documentCI() Delta input capacitance. t(su) Sum of the setup-time skew parameters t(h) Sum of the hold time skew parameters3 Device standard3.1 DescriptionThis PLL Clock Buffer is designed for a VDDQ of 1.8 V, an AVDDof 1.8 V and differential data input and output levels. Package options include a p
13、lastic 52-ball VFBGA and a 40-pin VFQFPN.The device is a zero delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pair of clock outputs (Y0:9, Y0:9) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input c
14、locks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FBOUT/FBOUT) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or
15、 VDDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on Y7/Y7 (they are free running in addition to FBOUT/FBOUT). When AVDDis grounded, the PLL is turned off and bypassed for test purposes.When both clock signals (CK, CK) are logic low, the device will enter
16、a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic low to being differen
17、tial signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FBIN, FBIN) and the input clock pair (CK, CK) within the specified stabilization time tL.The PLL in the CUA877 and CU2A877 clock drivers uses the i
18、nput clocks (CK, CK) and the feedback clocks (FBIN, FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y0:9, Y0:9). The CUA877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.The CUA877 is characterized for operation from 0oC to 70 oC.JEDEC Stand
19、ard No. 82-18APage 23.1 Description (contd)TopviewFigure 1 52-Ball VF-BGA (10x6 Array, 7.0x4.5 mm Body Size, 0.65 mm Pitch, MO-225 Variation BA) package pinoutsFigure 2 40-pin HP-VFQFP-N (6.0x6.0 mm Body Size, 0.5 mm Pitch, MO-220, variation VJJD-2, E2 & D2 nominal = 2.9 mm +/- 0.15 mm) package pino
20、utsGND GND GND Y6Y2 GND NB NB GND Y7Y2 VDDQ VDDQ OS Y7CK NB NB FbinVDDQ NB NB OE FbinVDDQ VDDQ VDDQ VDDQ FboutAVDD GND GND FboutGND GNDY1VDDQVDDQCKAGNDGNDY3NBNBY8Y6Y1 Y0 Y5 Y5Y0612 453CDEHBFGJAY3K Y4 Y9 Y9 Y8Y4BGAVDDQGNDGNDVDDQ1234567891011 12 13 14 15 16 17 18 19 202122232440 39 38 37 36 35 34 33 3
21、2 31302928272625 FBOUTVDDQFBINFBINY7Y9 Y8 Y8FBOUTY7Y6Y6Y1VDDQY9VDDQGNDY5Y5Y0 Y0AVDDVDDQAGNDCKY2Y2Y3Y3 Y4Y4CKVDDQVDDQOSOEY1GNDVDDQVDDQJEDEC Standard No. 82-18APage 33.2 Terminal functions3.3 Function table* L(Z)means the outputs are disabled to a low state meeting the IODLlimit in Table 5.Table 1 Ter
22、minal FunctionsTerminalNameDescriptionElectricalCharacteristicsAGND Analog Ground GroundAVDDAnalog power 1.8 V nominalCKClock input with a (10K-100K Ohm) pulldown resistor Differential inputCK Complementary clock input with a (10K-100K Ohm) pulldown resistor Differential inputFBIN Feedback clock inp
23、ut Differential inputFBIN Complementary feedback clock input Differential inputFBOUT Feedback clock output Differential outputFBOUT Complementary feedback clock output Differential outputOE Output Enable (Asynch) LVCMOS inputOSOutput Select (tied to GND or VDDQ)LVCMOS inputGND Ground GroundVDDQLogic
24、 and output power 1.8 V nominalY0:9 Clock outputs Differential outputsY0:9 Complementary clock outputs Differential outputsNB No ballTable 2 Function tableInputs OutputsPLLAVDDOE OS CK CK YYFBOUT FBOUTGND H X L H L LHBypassed/OffGND H X H L HL LBypassed/OffGND L H L H*L(Z)*L(Z) LHBypassed/OffGND L L
25、 H L*L(Z),Y7 active*L(Z),Y7 activeHLBypassed/Off1.8V(nom) LHLH*L(Z)*L(Z) LHOn1.8V(nom) LLHL*L(Z),Y7 active*L(Z),Y7 activeHL On1.8V(nom) HXLHLHLHOn1.8V(nom) HXHLHLHL On1.8V(nom) XXLL*L(Z)*L(Z)*L(Z)*L(Z)Off1.8V(nom) X XHH ResrvedJEDEC Standard No. 82-18APage 43.4 Logic diagramFigure 3 Logic diagram (p
26、ositive logic)Y8Y8Y7Y7Y6Y6Y5Y5Y4Y4Y3Y3Y2Y2Y1Y1Y0Y0Y9Y9FBOUTFBOUTPowerdownControl andTest LogicAVDDCKFBINCKFBINPLLOELD* or OEPLL bypassLD*LD*, OS or OEOS* The Logic Detect (LD) powers down the device when alogic low is applied to both CK and CK.GND10K-100kJEDEC Standard No. 82-18APage 53.5 Absolute m
27、aximum ratingsTable 3 Absolute maximum ratings over operating free-air temperature range (see Note 1)Supply voltage range, VDDQor AVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 2.5 VInput voltage range, VI(see Notes 2 and 3) . . . . . . . . . . . .
28、. . . . . . . . . . . . . . . . . . . .0.5 V to VDDQ+ 0.5 VOutput voltage range, VO(see Notes 2 and 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDDQ+ 0.5 VInput clamp current, IIK(VIVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
29、0 mAOutput clamp current, IOK(VOVDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous output current, IO(VO= 0 to VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mAContinuous current through each VDDQor GND. . . .
30、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mAStorage temperature range, TSTG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 C to 150 CNOTE 1 Stresses beyond those listed under “absolute maximum ratings” may cau
31、se permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect devi
32、ce reliability. NOTE 2 The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.NOTE 3 This value is limited to 2.5 V maximum.3.6 Recommended operating conditionsNOTE 1 The PLL is turned off and bypassed for test purposes when AVDDis grounded. D
33、uring this test mode, VDDQremains within the recommended operationing conditions and no timing parameters are guaranteed.NOTE 2 VIDis the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12 for definition. For CK and CK the VIHand VILlimits are used to
34、define the DC low and high levels for the logic detect state. Table 4 Recommended operating conditions (see Note 1)Min Nom Max UnitVDDQOutput supply voltage 1.7 1.8 1.9 VAVDDSupply voltage See Note 1VDDQVILLow-level input voltage, see Note 2OE, OS, CK, CK0.35 x VDDQVVIHHigh-level input voltage, see
35、Note 2OE, OS, CK, CK0.65 x VDDQVIOHHigh-level output current, See Figure 5CUA877 - 9mACU2A877 - 18IOLLow-level output current, See Figure 5CUA877 9mACU2A877 18VIXInput differential-pair cross voltage(VDDQ/2)-0.15 (VDDQ/2)+0.15VVINInput voltage level - 0.3VDDQ+ 0.3VVIDInput differential voltage,See N
36、ote 2 and Figure 12DC 0.3VDDQ+ 0.4VAC 0.6VDDQ+ 0.4VTAOperating free-air temperature 0 70 CJEDEC Standard No. 82-18APage 63.7 DC specificationsNOTE 1 Total IDD= IDDQ+IADD= FCK* CPD* VDDQ, solving for CPD= (IDDQ+IADD)/(FCK*VDDQ) where FCKis the input Frequency, VDDQis the power supply and CPDis the Po
37、wer Dissipation Capacitance.Table 5 Electrical characteristics over recommended operating free-air temperature rangePARAMETER TEST CONDITIONSAVDD, VDDQMIN TYP MAX UNITVIKAll inputs II= 18 mA1.7 V -1.2 VVOHHigh output voltageIOH= 100 A1.7 to 1.9 VVDDQ-0.2VIOH= 9 mACUA8771.7 V 1.1IOH= 18 mA CU2A877VOL
38、Low output voltageIOL= 100 A1.7 to 1.9 V 0.1VIOL= 9 mA CUA8771.7 V 0.6IOH= 18 mA CU2A877IODLOutput disabled low currentOE = L, VODL= 100mV1.7 V 100 AVODOutput differential voltage, the magnitude of the difference between the true and complimentary outputs, see Figure 12 for definition.1.7 V 0.6 VIIC
39、K, CKVI= VDDQor GND1.9 V 250AOE, OS, FBIN, FBINVI= VDDQor GND1.9 V 10IDDLDStatic supply current, IDDQ+ IADDCK and CK = L 1.9 V 500 AIDDDynamic supply current,IDDQ+ IADD, see Note 1 for CPDcalculationCK and CK = 410 MHz,all outputs are open (not connected to a PCB)1.9 V 300 mACICK and CK VI= VDDQor G
40、ND1.8 V23pFFBIN and FBINVI= VDDQor GNDCI()CK and CKVI= VDDQor GND0.25FBIN and FBINVI= VDDQor GND0.25JEDEC Standard No. 82-18APage 73.8 Timing requirementsNOTE 1 The PLL must be able to handle spread spectrum induced skew.NOTE 2 Operating clock frequency indicates a range over which the PLL must be a
41、ble to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.)NOTE 3 Application clock frequency indicates a range over which the PLL must meet all timing parameters.NOTE 4 Stabilization time is the time required for the integrated PLL circuit to
42、 obtain phase lock of its feedback signal to its reference signal, within the value specified by the Static Phase Offset t(), after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its re
43、ference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Table 6 Timing requirements over recommended operating free-air temperature range.AVDD,
44、VDDQ= 1.8 V 0.1 VUNITMIN MAXfCKOperating clock frequency (see Notes 1 and 2) 125 410 MHzApplication clock frequency (see Notes 1 and 3) 160 410 MHztDCInput clock duty cycle 40 60 %tLStabilization time (see Note 4) 15 sJEDEC Standard No. 82-18APage 83.9 AC specificationsNOTE 1 Static Phase Offset doe
45、s not include Jitter.NOTE 2 Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.NOTE 3 The Output Slew Rate is determined from the IBIS model into the load shown in Figure 4. It is measured single ended.NOTE 4 VOXspecified at t
46、he DRAM clock input or the test load.Table 7 Switching characteristics over recommended operating free-air temperature range(unless otherwise noted)(see NOTE 6)DESCRIPTION DiagramfCK(MHz)AVDD, VDDQ= 1.8 V 0.1 VUNITMIN Nom MAXtenOE to any Y/Y see Figure 14 160 to 410 8 nstdisOE to any Y/Y see Figure
47、14 160 to 410 8 nsslr(i)Output Enable (OE) see Figure 12 160 to 410 0.5 V/nsInput clock slew rate, measured single ended.see Figure 12 160 to 410 1 2.5 4 V/nsslr(o)Output clock slew rate, measured single ended. (see Notes 3 and 5)see Figures 4 and 12160 to 410 1.5 2.5 3 V/nsVOXOutput differential-pa
48、ir cross- voltage, (see Note 4)see Figure 5160 to 410(VDDQ/2) - 0.1(VDDQ/2) + 0.1Vtjit(cc+)Cycle-to-cycle period jitter see Figure 7 160 to 410040pstjit(cc-) 0 -40 pst()Static phase offset(see Note 1)see Figure 8 160 to 410 -50 50 pst()dynDynamic phase offset (see Note 7)see Figure 13160 to 270 -50
49、50 ps271 to 410t()dyn(min)t()dyn(max)pstsk(o)Output clock skew(see Note 7)see Figure 9160 to 270 40 ps271 to 410tsk(o)maxpstjit(per)Period jitter (see Notes 2 and 7)see Figure 10160 to 270 -40 40 ps271 to 410tjit(per)mintjit(per)maxpstjit(hper)Half-period jitter(see Note 2)see Figure 11160 to 270 -75 75 ps271 to 410 -50 50 ps t(su)|tjit(per)| + |t()dyn| + tsk(o) (see Note 7)271 to 410 80 ps t(h)|t()dyn|+ tsk(o)(see Note 7)271 to 410 60 psThe PLL in the CUA877 and CU2A877 must be capable of meeting all the abov
